GigaBee LX150 MIG map error

[maxbuder]

Hello,

do you have a working reference design using both RAMs for the LX150 version?
I am experiencing a map error, that I have posted on the Xilinx forum.

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/S6LX150-and-MIG-3-6-1-with-two-MCBs-chrashes-during-map/td-p/199909

Searching google I found a there is a log file online that covers excactly the same error that uses also the same hardware.

Do you have any ideas on this topic.

Thank you and with best regards
Max

https://svn.eldesi.com/svn/eldesi/TE-ReferenceDesigns/GigaBee-ISE/branches/GigaBee_XC6SLX-webserver-ISE_12_4/system.log

[Ales Gorkic]

Dear Max,

We have one working design with ll_temac ethernet and dual MCBs for LX150.
It is on the new trenz SVN and was developed with EDK v12.
Lately we developed similar with AXI architecture.
The major problem at the beginning was pll placement and pll lock signal routing.
As I remember it uses one PLL for 625MHz clock generation. The lock signal from this pll needs to be routed directly to MCB plls.

You can take this design for a reference.

Maybe you have also some problems with IOSTANDARD definition for unconstrained MCB signals (ZIO, RZQ).

Best regards,

Ales

[rifo]

Hello Max,

I see that you have already found the solution to your problem on Xilinx forums. There is a small design of mine in the SVN repository with the name ...MIG-Rifo. Following the same approach as you, I have also made use of a Bufio2 before feeding incoming clock to MCB PLLs and everything mapped fine.  Just wanted to note this here so that others may benefit it in the future.