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TE0820 system device tree question on test_board reference design

Started by DR, May 03, 2022, 05:44:28 PM

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DR

Hello Everyone,

I have been working with the test_board reference design for the TE0820 for a few weeks now
Using Vivado 2021.2 and Petalinux 2021.2

Ran into a couple questions about the system device tree in "system-user.dtsi"

1) For the SD0 eMMC entry, I see:
              // disable-wp
    which implies that the write protect is not disabled - However I am able to format and wrote to the eMMC device.
    How is this possible?

2) The SD0 eMMC entry also shows:
            no-1-8-v
    Again, this implies that the eMMC should be running at 3.3V. However, when I look at the schematic, I see it is connected to Bank 500 which is a 1.8V bank
    Also - the SDINBDG4-8G NAND chip uses 1.8V for VCCQ
    I would like to understand why the SD0 eMMC entry is set for no-1-8-v?

3) The SD1 sd2.0 entry shows no-1-8-v, which makes sense, since this SDIO bus is on BANK 501 and 3.3V
    However, the TE0701 uses a voltage translator U2 from 1.8v to 3.3v running from VIOB which is 1.8v on JM1
    I don't understand how the voltage translator could be working? i.e. the FPGA side will be getting 1.8v from the translator?

Thank you for your help.
Dave

JH

Hi,
Quote1) For the SD0 eMMC entry, I see:
              // disable-wp
    which implies that the write protect is not disabled - However I am able to format and wrote to the eMMC device.
    How is this possible?
That's a question to xilinx :-)
Maybe this will be ignored. Did you translate final dtb back dts and check if it was add there?
Quote
2) The SD0 eMMC entry also shows:
            no-1-8-v
    Again, this implies that the eMMC should be running at 3.3V. However, when I look at the schematic, I see it is connected to Bank 500 which is a 1.8V bank
    Also - the SDINBDG4-8G NAND chip uses 1.8V for VCCQ
    I would like to understand why the SD0 eMMC entry is set for no-1-8-v?
In the past some customer has detected sometime linux access problem and this property has solved this(I don't know why)....maybe it's not longer needed.
QuoteThe SD1 sd2.0 entry shows no-1-8-v, which makes sense, since this SDIO bus is on BANK 501 and 3.3V
    However, the TE0701 uses a voltage translator U2 from 1.8v to 3.3v running from VIOB which is 1.8v on JM1
    I don't understand how the voltage translator could be working? i.e. the FPGA side will be getting 1.8v from the translator?
See note:https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Carriers#id-4x5SoMCarriers-TE0701
TE0701 was original design for our 7 series Zynq module which use 1.8V. On the next PCB update it's planned to add jumper for voltage selection...
br
John