TE720 pin state during/after startup

[linasr]

Dear All,

I have multiple SPI masters in my system. One of them is TE720 module using SPI 0 block with EMIO pins and other is "normal" AXI Quad SPI. Microprocessor SPI masters share the same SPI buses and pins. I am afraid, that microprocessor and ZynQ might have a conflict. I found PCN-20210127 note stating this:

#1 Added generic options for PUDC and Boot Mode

Type: Enhancement
Reason: Provide easy option to select pullup/down for CPLD IO pins connected to Zynq Boot Mode and PUDC pins.
Impact: None. Default CPLD source code is still PUDC low (Zynq pullups activated) and Boot Mode QSPI/SD.

So during the startup all the pins of ZynQ have PULLUP enabled. But what happens later before my code starts the main() function (it's bare metal application)? Do the pins stay tristated without PULLUP until I do my system probing and setup SPI directions? The relevant pins are declared as INOUTs my project.

Thank you,
Linas

[JH]

Hi,

So during the startup all the pins of ZynQ have PULLUP enabled. But what happens later before my code starts the main() function (it's bare metal application)? Do the pins stay tristated without PULLUP until I do my system probing and setup SPI directions? The relevant pins are declared as INOUTs my project.

Before bitstream is configured, IOs will be pulled up with def. CPLD Firmware, after bitstream is configured with your bitstream it will be do what you has configured in your design, when you use PS SPI, see Zynq IP configuration.

br
John