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Started by engkan2kit, June 04, 2021, 10:12:11 AM
QuoteI'm just patching the fsbl from petalinux.
QuoteI'll try to setup a Vitis Workspace to do a memory test over the debug console. I had a Vitis workspace before but the flow takes to long just to generate the FSBL so I had to move it to petalinux.
QuoteI'm having trouble using the script for 2019.2. I only have 2019.2 installed in my machine. There is an error when creating a project in vivado related to current_design_bd that the block design must be open or created when running a certain command. But it's just still creating the project.
QuoteThis has no problem. but one thing I noticed is that in the half-ram build, the TE0820 TE_XFsbl_HookPsuInit_Custom was not there. In the half-ram, it prints directly to Xilinx Zynq MP First Stage Boot Loader (TE modified).
QuoteI can't use the debugger of vitis on the TE0820 for the fsbl right since I can't boot from jtag? I can debug this quickly if I can boot from JTAG.
Quote from: JH on September 28, 2021, 08:09:04 AMHi,which Vivado/Vitis version did you use?I've test it one time on my place and it works.I've use our 2020.2 design:https://wiki.trenz-electronic.de/display/PD/TE0820+Test+Board1. create the project with the selection guide and 2020.22. open Block Design and select the ZynqMP IP --> go to memory and change effective dram bus width to 163. Generate bitstream -> use console and type TE::hw_build_design -export_prebuilt4. Start Vitis generation with our scripts: TE::sw_run_vitis -alluse the new generated Hello TE0820 boot.bin from your assembly variant and boot from SD(is faster, QSPI should also work)brJohn
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