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Started by Dehim, February 26, 2020, 03:20:32 PM
Quote[Place 30-68] Instance IBUFDS_GTE4_inst (IBUFDS_GTE4) is not placed
Quote[Vivado 12-1411] Cannot set LOC property of ports, Site PS8_X0Y0 is not part of a diff pair
Quote[Place 30-640] Place Check : This design requires more BUFG_GT cells than are available in the target device. This design requires 1 of such cell types but no compatible site is available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.
Quoteset_property PACKAGE_PIN E21 [get_ports gtr_clk_1_p]set_property PACKAGE_PIN E22 [get_ports gtr_clk_1_n]
QuoteA 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.
Quote[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IBUFDS_inst/O] > IBUFDS_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X2Y99 s_se_clk_BUFG_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y47 The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances. Clock Rule: rule_bufgce_bufg_conflict Status: PASS Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be used at the same time and s_se_clk_BUFG_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y47
Quote[DRC CKLD-2] Clock Net has IO Driver, not a Clock Buf, and/or non-Clock loads: Clock net IBUFDS_inst/util_ds_buf_0/U0/USE_IBUFDS.GEN_IBUFDS.IBUFDS_I/O is directly driven by an IO rather than a Clock Buffer or may be an IO driving a mix of Clock Buffer and non-Clock loads. This connectivity should be reviewed and corrected as appropriate. Driver(s): IBUFDS_inst/util_ds_buf_0/U0/USE_IBUFDS.GEN_IBUFDS.IBUFDS_I/IBUFCTRL_INST/O
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