Using Vivado ILA with TE0820 on TE0706

[mrguy07]

Hello,

I've been working with two of the TE0820 series boards (CG and EV) mounted to the TE0706 carrier board. After inserting a few lines in the devicetree to get the SD card working in linux - all was well.

I have a custom HDL design running in the FPGA and communication up with the arm cores. I went to insert an ILA core using the 'Setup Debug' option in Vivado (2018.2) - as I have always done - but no matter what I try I'm not able to see this core in the Hardware manager. I am able to see the FPGA and arm_dap_1, but that is it.

Looking around I found someone on this forum who ran into a similar issue here: https://forum.trenz-electronic.de/index.php?topic=807.0

If I run 'report_debug_core' in my implemented design I see everything is there.

Perhaps the processor is not up after programming a bitstream, and this is why the cores can't be seen. I've also tried to manually bring up the arm system using xsct but this didn't work either.

I see the reference designs use the VIO core and that apparently works. I believe I've seen elsewhere on the internet that the VIO core works in some instances when people are struggling with the ILA. Is this why the VIO core is in the reference design and not an ILA? Having to use VIO instead of ILA would be a massive productivity hit as that core is very limited compared to the ILA tool.

I really like these trenz products and would like to use them on a number of systems at work. However, being able to use Vivado ILA is ESSENTIAL to any engineer working with these SOCs. So far the rigor involved in getting this working has been very frustrating. A similar Avnet product has the ILA core detected first try.

Please help me! I look forward to a solution to this so I can move forward with these trenz systems.

Thank you in advance!

[JH]

Hi,
there is no difference if you use ILA or VIO. Important is the reference CLK of the IP must be available.

Which reference CLK did you use for your ILA?
If you use PS-PL CLK, you must initialise PS. This is not done by bitstream programming only.
You must generate Boot.bin with FSBL and boot from SD or QSPI. Or you use Xilinx SDK to configure PS.
If PS is programmed and you use the same PS-PL CLKs (with the same frequency), you can reload also PL part only with Vivado(do not power off and PS should not try to get access to PL over AXI during programming time).

Did you checked netlist of the implemented design in the vivado floorplanner? Maybe your design was optimised and ila was removed again.

Did you try to instantiate ila directly on block design?

br
John

[mrguy07]

How foolish of me!

I guess in the process of debugging this I lost sight of the fact that the debug core was not getting implemented - very strange, but a vivado/me problem not a Trenz problem.

After rebuilding and double checking I am able to boot with linux running (PS-PL clock running) and detect the ILA core in vivado right away.

Sorry for false alarm. Great product!

[JH]

No problem, good that it works now.
br
John

[hectorh]

Hi John,

Can you please help me.
I also have a TE0820-02 3CG and the TE0706-03.

I am unable to run Linux and boot from SD card.

When I connect JTAG on the board I can see the FPGA and ARM CPU.

I have tried using the prebuilt images still I cannot boot on SD Card.

Regards,
BH Hlophe

[JH]

Hi BH,

I've answered you today on your email. So email or forum, what did you prefer?
br
John