Hello,
We are powering all Vin and Vin3_3 from the same 3.3 V power chip/IC. We will be using all 8 GTH lanes for JESD204b interface and the FPGA is expected to be 80% full. Also, we intend to the SDRAM on board. So, it would be very helpful to know the maximum (safe limit) current that our power chip should support for correct working of TE0841 (XCKU040) module ?
Also, if we use the 3.3_Vout and 1.8_Vout from the TE module itself to power up the VCCIO, then are there any limits/restrictions (current rating etc) that we should be aware of ?
Regards,
Raju
Hello,
you must use Xilinx Power estimator to calculate FPGA power consumption, see "What's is the maximum power consumption of the module?" of our FAQ:
- https://wiki.trenz-electronic.de/display/PD/FAQ
Ensure sufficient cooling is important.
3.3V_VOUT and 1.8V_VOUT can be used for VCCIO power. Both are connected to a 3A power regulator, but they supply also other components (see schematic).
- https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0841/REV01/Documents
Current limitation over connector pins is described here:
- http://suddendocs.samtec.com/catalog_english/lshm_dv.pdf
br
John