Hi,
I would like to reset the RPi Cam by a hard reset using the camera reset line.
My assumption (perhaps it's wrong) is that MIO52/53 are fed through the CPLD and their logic levels appear unchanged at CSI_GPIO0 and CSI_GPIO1 (which are used as CAM-Reset and CAM-LED control).
As a test I have tried to control the camera LED by SW. Without success. I am pretty (~85%) sure that my PS7-GPIO-Software works fine. At least, it has been succesfully tested in other Zynq environments.
1. Did anyone managed to control the LED and/or reset line of the camera?
2. Is there any additional magic that needs to be taken into account? (e.g. MIO52/53 are somehow gated in the CPLD)
Thanks in advance
Winfried
Hi Winfried,
In CPLD MIO53/53 are conected to GPIO like
CSI_IO0 <= MIO52;
CSI_IO1 <= MIO53;
I did't try to control camera LED, perhaps it requre some additional configuration via I2C.
Best regards
Oleksandr Kiyenko
Hi Oleksandr,
problem solved: Under Linux the GPIO clock is not enabled by default. As I haven't been using the standard GPIO driver, I had to enable it by setting bit 22 in the APER_CLK_CTRL register of the System Level Control IP (Address: 0xF800012C).
This is also explained here: https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Using-generic-uio-with-PS-GPIO/td-p/643734
Regards
Winfried