Text only | Text with Images

Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: jmadill on September 07, 2016, 08:13:54 PM

Title: TE0720 PUDC_B Pin
Post by: jmadill on September 07, 2016, 08:13:54 PM
Is there a way that I change change PUDC_B pin to be logic high? I need all the IO to be logic low when the device is being programmed upon startup.

Thanks,

James
Title: Re: TE0720 PUDC_B Pin
Post by: JH on September 08, 2016, 10:52:36 AM
Hi,

on TE0720, PUDC_B is controlled by the CPLD on the TE0720 (default configuration to logical zero).
Please write a request to our support (support@trenz-electronic.de), so we can send you a modified firmware for the cpld  with PUDC_B configured to logical high.

Br
John
Title: Re: TE0720 PUDC_B Pin
Post by: narinx on July 31, 2019, 01:50:54 PM
Hi,

I also need this functionality for the TE0720. I sent an email but don't ge any response..
Did the emailaddress change by any chance?

Br,
Hans
Title: Re: TE0720 PUDC_B Pin
Post by: Thorsten Trenz on July 31, 2019, 05:14:23 PM
Hi,
its vacation time, and we will process your email as soon as possible.
Please excuse the delay.


Best Regards,
Thorsten Trenz

Title: Re: TE0720 PUDC_B Pin
Post by: narinx on July 31, 2019, 05:45:52 PM
No problem, thanks! :-)
Br,
Hans
Text only | Text with Images