How can I have access to these devices from FSBL, "UBoot", "Stand Alone SW" and Linux?
- U10= ATSHA204A
- U17= 11AA02E48T
Are there any examples how to use them for example to de/encrypt rootfs?
Does it contain MAC-addresses for both Ethernetadapters?
Any further documentation beside Trenz-schematic and datasheet from vendors?
Hello,
MAC address from U17 is readed automatically in SC CPLD and then readed by software in FSBL. You can found code in our FSBL example (files fsbl_hooks.c TE0720-02.c TE0720-02.h)
You can access U10 chip from FPGA fabric (Signals X3(FPGA pin N15) X2(FPGA pin M15)), corresponding bits SC register CR2 should be set. See https://wiki.trenz-electronic.de/display/TE0720/SC+Firmware+ver+0.02
Unfortunatelly we don't have complete software example for this chip.
Best regards
Oleksandr Kiyenko
Thank you for these informations!
I think you are talking about the FSBL-patches inside
http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/TE0720-GigaZee/reference_designs/2014.4/TE0720-02-hdmi.zip
??
TE0720-02.c TE0720-02.h are missing, but there are are te_fsbl_config.h, te_fsbl_hooks.c, .h
Btw.
http://www.trenz-electronic.de/download/d0/Trenz_Electronic/d1/TE0720-GigaZee/d2/reference_designs/d3/2015.2.html
does not include these files.
N15 and M15 are signals X3 and X2 connected to CPLD.
SC register CR2 means Control Register 2; XIO Control
I can read this with
Status = XEmacPs_PhyRead(&Emac, 0x1A, 6, &rval16)
??
Where can I find a bit description of these control-registers
??
Which bit should be set to enable U10?
So after enabling corresponding bits SC register CR2 I should be able to read U10
I have to connect an IIC to cpld_x2 and 3 in PL like the SC ist connected in your SC-IP-core to cpld_x1 and 7 (for communication with RTC)
??
So the SC makes a conversion from IIC to the Single-Wire-Interface of U10
??
Hello
I add some additional registers and pins description to https://wiki.trenz-electronic.de/display/TE0720/SC+Firmware+ver+0.02
Best regards
Oleksandr Kiyenko