I have a little problem with a video data stream which should be stored in memory .
Some facts:
video input bandwidth: 8 bit
video clk: 115 Mhz
resolution: 1280 x 1024
pixelclock, hsync, vsync, 8 bit video data are the inputs
The attached image shows a part of the block diagram.
Is it necessary to connect the vid_blanks and active video?
Which clock should be used at v_vid_in_axi4s_0 aclk pin?
I get no reaction at vtd_vsync and m_axis_video_tuser pin while video source is present
Thank you very much
I believe the Video to Stream module needs either the blanks or a composite active video signal to know when valid data is present (only valid data is put on the stream, not data during blanking).
aclk will be the clock for the stream. Normally it is at least as fast as your video coming in. You can go slightly lower with sufficient fifos configured, as it can catch up during blanking (which is one reason it needs the blanking/active signals).