Hi everyone, I'm working with a TE0820-05-4AE21FA module on a TE0706-06 carrier board using Vivado/Vitis 2024.2. The original Trenz reference design boots correctly from a FAT32 SD card and gives the expected UART output, but after creating a small custom Vivado design with the Zynq UltraScale+ PS and an AXI GPIO peripheral, my new BOOT.bin behaves differently. I generated the XSA, FSBL, PMU firmware, bitstream and application from the new design and placed them in the boot image, but although the FSBL initialization messages appear over UART, the PL does not seem to be programmed correctly and I cannot reliably access the AXI GPIO from Vivado Hardware Manager. I have compared the PS and DDR configuration with the reference project, checked the TE0820 board files and part selection, regenerated the FSBL and PMU firmware, verified the bitstream and implementation, checked the SD formatting and boot-mode switches, and confirmed that restoring the original reference BOOT.bin makes the board work normally again. I'm wondering if there are any TE0820-specific PS, FSBL or boot-image settings that must be preserved when creating a custom design with Vivado 2024.2. Also, is there a recommended way to verify from the UART or Vivado Hardware Manager that the PL bitstream was actually loaded during SD boot? I can provide the Vivado project configuration, XSA, BOOT.bin partition information, UART log and switch settings if those would help troubleshoot the issue.
Basketball Bros (https://basketballbrosgame.org)