Hello Trenz Team,
I am replacing our existing SoM with TE0823-02-3PIT1MA. The same carrier board and SD boot setup work with our old SoM (with same Zynq UltraScale+ device/part).I have checked the TE0823 schematic and verified that the required power rails are present.
On the TE0823:
All required power rails are present.
PS_REF_CLK = 33.33 MHz
PS_POR_B = 1.8 V
U4 (BD39040MUF-CE2) VDD = 3.3 V
RSTIN = 0.85 V
DIN1–DIN4 ≈ 0.8 V as expected from the resistor dividers
WDEN = 0 V
XRSTOUT (pin 15) = ~0.02 V and stays LOW continuously
PG_ALL = ~0.017 V
No SD clock activity and no UART boot logs.
I have tried both states of the carrier-board boot-mode pin.
Could you please confirm:
1. Can XRSTOUT/PG_ALL remaining LOW prevent the ZynqMP from booting?
2. If all DIN1–DIN4, RSTIN, and VDD are correct, why could U4 still keep XRSTOUT LOW?
3. Does the TE0823 CPLD require PG_ALL to be HIGH before allowing normal ZynqMP startup?
Thanks.
Hallo. Which carrier do you use? Are you sure U4 (BD39040MUF-CE2) VDD = 3.3V? Or RSTIN = 0.85V?
Because RSTIN = 0.85V says that 3.3VIN = 3.5V
Best regards, Maksim Tserabei