Print Page - TE0728 - DDR Settings

Title: TE0728 - DDR Settings
Post by: chutson on January 22, 2026, 05:23:28 PM

Hello,

Looking at the test_board example, the DDR is set to DDR3L and the MT41J256M16 RE-125. In the schematic it is using 1.5V as the supply (instead of 1.35V for DDR3L) and there is a different part number NT5CC256M16CP-DI. Are we advised to use the settings from the test_board example? There is some mismatch between that and the datasheet.

Thanks,
Chris

Title: Re: TE0728 - DDR Settings
Post by: chutson on January 22, 2026, 06:40:10 PM

Compared to the defaults from the test_board using MT41J256M16 RE-125 I believe the following changes are needed.

DDR3L -> DDR3
tRC = 48.91ns -> 50.625ns
tRASmin = 35ns -> 37.5ns
tFAW = 40ns -> 50ns

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Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: chutson on January 22, 2026, 05:23:28 PM