Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: remy on December 29, 2025, 02:16:53 PM

Title: Description of pins on TE0728
Post by: remy on December 29, 2025, 02:16:53 PM
Hi,

I'm making m y own carrier board to the TE0728 SoC Module and I'm not able to find description for the following pins:
J1.12 INTB
J1.14 RSTB
J1.16 FS0B
J1.15 MUX_OUT
J1.17 VCCA
J1.18 DEBUG
J1.20 LIN
J1.21 VSUP3_LIN

Would it be possible to get some inside into what these pins should/could/must be used for?

Thanks,
Title: Re: Description of pins on TE0728
Post by: Antti Lukats on December 29, 2025, 04:40:21 PM
Hi,

if you look at schematic you see a RED CROSS on those wires, this is Altium desiger marking for exclusion from rules checking. This means that altium DRC passes and does not report single pin nets as error.

There is no internal connection on the board on those pins, you can simple ignore them, they used to be connected to some weird security chip in PCB rev 01
Title: Re: Description of pins on TE0728
Post by: remy on December 30, 2025, 10:21:01 AM
Understand, I will ignore them. Thank you!