Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: guirenaud on September 04, 2025, 10:49:11 AM

Title: [TEI0006-04-API23A]: GX transceivers clock
Post by: guirenaud on September 04, 2025, 10:49:11 AM
Hello

We'll use the SOM TEI0006-04-API23A for a new development projects.
In one of them we'll use all GX Transceivers with SFP+ connexions running at 12.5Gbps. We are considering using 10GBase-R protocol with ATX PLLs.
The MAX10 is programming the clock generator (SI5345A) with default values as described on the Trenz wiki page:
TEI0006 firmware for Intel MAX 10 (https://wiki.trenz-electronic.de/display/PD/TEI0006+Intel+MAX+10)

I've got questions:

Is the MAX10 firmware is customizable by the customer (especially to set the user clock outputs from the programable oscillator) ? I guess yes but it s just for confirmation

Is it possible to achieve data rates up to 12.5Gbps with in single REFCLK_GX input for all of the 12 GX Channels? With one of the default clock values coming into REFCLK_GX Bank 1D, these are outputs 6 (100MHz) or 7 (125MHz) from programmable oscillator. Which clock frequency input would be recommanded for that case ? Maybe 156.25MHz ?

Best regards

Guillaume
Title: Re: [TEI0006-04-API23A]: GX transceivers clock
Post by: RC on September 05, 2025, 04:13:47 PM
Hello,
We can to share the MAX10 source code with you. You can modify it as needed for your application.
Please email support@trenz-electronic.de so we can send the files as attachments.

According to UG-20070, one refclk can drive multiple channels.

Based on the ATX PLL configuration GUI, 125 MHz should still work well as a reference clock at 12.5 Gbps.

Please feel free to contact us if you encounter any issues.
Title: Re: [TEI0006-04-API23A]: GX transceivers clock
Post by: guirenaud on September 16, 2025, 09:53:12 AM
Thanks for your quick feedback !