Print Page - CPLD Power Sequencing Timing – TEBF0818 Carrier Board (Request for Source Code)

Title: CPLD Power Sequencing Timing – TEBF0818 Carrier Board (Request for Source Code)
Post by: Rudraksh on August 01, 2025, 08:58:51 AM

Hi all,

I'm working with the TEBF0818 carrier board and need clarity on how the CPLD handles power sequencing, particularly the timing between each power rail enable signal after the PWR_GOOD signal is asserted.

Unfortunately, I couldn't find the CPLD firmware or source code in the provided Trenz reference materials.

I'd appreciate any insights on the following:

Are the enable signals triggered with fixed delays, or are they driven based on monitoring power-good feedback from each rail?

Can someone please share the CPLD source code or constraints file used for managing power sequencing on the TEBF0818?

I have already reviewed this page:
👉 TEBF0818 CPLD Firmware Wiki (https://wiki.trenz-electronic.de/display/PD/TEBF0818+CPLD+Firmware)
But it doesn't provide any details regarding the timing between enable signals.

Any help, waveform examples, or pointers to documentation would be greatly appreciated.

Thanks in advance!

Title: Re: CPLD Power Sequencing Timing – TEBF0818 Carrier Board (Request for Source Code)
Post by: M Kirberg on August 01, 2025, 02:21:38 PM

Hi,

you will find it in the download folder, also the source code
https://www.trenz-electronic.de/Downloads/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/5.2x7.6_Carriers/TEBF0818/REV02A/Firmware

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Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: Rudraksh on August 01, 2025, 08:58:51 AM