Hello,
I want to create an IP core using the HDL coder in MATLAB Simulink. It's working so far. When I create the IP core, my outputs switch at a different frequency than in the MATLAB simulation. Depending on the settings I use, I'm sometimes closer to the simulation or further away. However, I haven't been able to find the exact frequency after experimenting. I've used the following settings see in the pictures. Are there any "reference settings" for this, or what parameters could be causing the problem? The CLK for the IP core in Vivado is set to 250 MHz (same as the settings in MATLAB). The Simulink model is divided into an embedded C part and an FPGA part. The settings for the C part shouldn't play a role in the IP core generation? Can anyone help, or has anyone already done this? advisorSettings.PNG.
Hi,
our experience with MatLab/Simulink is very limited. If you think it is a problem of the settings MatLab/Simulink support should be your fist choice.
I can give only very general advice like: Check design clock source frequencies in hardware compared to simulation.