Hi
I choose TE0600-GigaBee_XC6LX-Axi-EDK-13.2-v1.0.f79134d.zip as a start point for my design,
I have EDK 13.4. So I upgraded the whole desin except axi_ethernet and axi_dma.
I've implemented design for xc6lx150.
when I program board with generated download.bit,everything is fine.
By raw_apps.elf I can ping board, run http server and echo server, I haven't tested iperf test yet.
But when I try to test the memory of system by using memory_test application of SDK I have problem,
All of tests on MCB3_DDR is OK. But the result of mem_test application on MCB1_DDR3 is FAILED.
--Starting Memory Test Application--
NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: MCB3_DDR3
Memory Controller: axi_s6_ddrx
Base Address: 0xc0000000
Size: 0x08000000 bytes
32-bit test: PASSED!
16-bit test: PASSED!
8-bit test: PASSED!
Testing memory region: MCB1_DDR3
Memory Controller: axi_s6_ddrx
Base Address: 0xd0000000
Size: 0x08000000 bytes
32-bit test: FAILED!
16-bit test: FAILED!
8-bit test: FAILED!
--Memory Test Application Complete--
I would be so appropriate of your help
Hi
Regardless of software cache settings hardware should be configured to correct access. In this example MCB1 is not in cash region.
Change MHS settings to
BEGIN microblaze
...
PARAMETER C_ICACHE_BASEADDR = 0xc0000000
PARAMETER C_ICACHE_HIGHADDR = 0xcfffffff
PARAMETER C_DCACHE_BASEADDR = 0xc0000000
PARAMETER C_DCACHE_HIGHADDR = 0xcfffffff ...
END
BEGIN axi_s6_ddrx
PARAMETER INSTANCE = MCB3_DDR3
...
PARAMETER C_S0_AXI_BASEADDR = 0xc0000000
PARAMETER C_S0_AXI_HIGHADDR = 0xc7ffffff ...
END
BEGIN axi_s6_ddrx
PARAMETER INSTANCE = MCB1_DDR3
...
PARAMETER C_S0_AXI_BASEADDR = 0xc8000000
PARAMETER C_S0_AXI_HIGHADDR = 0xcfffffff ...
END
and regenerate linker script
Best regards
Oleksandr Kiyenko
Hi Oleksandr Kiyenko
I checked system.mhs and Its configuration is according your reply.
I attach my syste,.mhs.
Thanks Alot
Hi Razi
Sorry, I made mistake in my post. I edit it to correct values now
Microblaze cache region should contain both memory controllers 0xc0000000 - 0xcfffffff. To avoid gap address of second controller should be changed to 0xc8000000-0xcfffffff
Best Regards
Oleksandr Kiyenko
Hi Oleksandr
I was in vacation for awhile. :)
I changed system.mhs according your advice and It's working.
Thanks.