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Title: TEF1001 CPLD default PLL config
Post by: ster on May 06, 2025, 03:30:33 PM

Hi, I'm bringing up TEF1001-03-B2IX4-K. I would like to use integrated PLL to generate clocks for PL, but it seems like none of clocks are enabled by default, except 200 MHz for DRAM bank (at least nothing is mentioned in TRM or CPLD firmware description)

Do I miss something or how am I supposed to configure PLL with I2C without any initial clock? Or am I supposed to use DRAM clock?

Thanks a lot in advance :)

Title: Re: TEF1001 CPLD default PLL config
Post by: JH on May 12, 2025, 12:07:03 PM

Hi,
we have a reference design online where SI5338 will be configured on power up:
https://wiki.trenz-electronic.de/display/PD/TEF1001+Test+Board
I2C Interface and configuration is included in the bootloader source code of the design. Register header file (te_SI5338-Register.h) can be created with Clock builder pro from skyworks.

br
John

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Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: ster on May 06, 2025, 03:30:33 PM