Do you have an example of a PCIe Block Design for the TEF1002 + Kintex UltraScale (KU040) fpga?
In the thread https://forum.trenz-electronic.de/index.php?topic=1300.0 there is a similar question for TEF1001, where you refer to the example design https://wiki.trenz-electronic.de/display/PD/TEF1001+Test+Board.
However, this uses a 7 Series fpga, where the AXI bridge macro "AXI Memory Mapped to PCI Express Gen2" is instantiated. However I cannot see its connection to any PCIe hard IP. I was expecting 4 AXI4-Stream interfaces, which the PCIe hard IP uses, but cannot see these anywhere in the TEF1001 Block Design.
In my case I am looking for an example of the connection of the "DMA/Bridge Subsystem for PCI Express" soft IP to the "UltraScale Devices Gen3 Integrated Block for PCIe" hard IP.
Quote from: axelbb@dtu.dk on April 16, 2025, 09:23:15 AMDo you have an example of a PCIe Block Design for the TEF1002 + Kintex UltraScale (KU040) fpga?
No, we do not have it. We can not have reference designs for all possible combinations of modules and baseboards. AMD documentation should explain the PCIe usage with Ultrascale.