Trenz Electronic GmbH Support Forum

Trenz Electronic Products => UltraScale => Topic started by: hahmed on December 10, 2024, 12:35:09 PM

Title: TE0818+TE0813
Post by: hahmed on December 10, 2024, 12:35:09 PM
Hi
I am currently using these boards with Vivado 2024.1.
I am trying to find a free running CLOCK where I can develop my design on PL logic.

The page 17 of SCH-TE0813-02-4AE81-A.pdf shows all clocks are going to MGT. These clocks are dedicated ones.

I tried to use A21 (clk_in_p) and A22(clk_in_n) to feed into IBUFDS

--IBUFDS_inst : IBUFDS
--port map (
--   O => CLK,   -- 1-bit output: Buffer output
--   I => clk_in_p,   -- 1-bit input: Diff_p buffer input (connect directly to top-level port)
--   IB => clk_in_n  -- 1-bit input: Diff_n buffer input (connect directly to top-level port)
--);


It does not like it.

Then, I commented out and try to debug a signal using

debug_0: ila_0
PORT MAP (
clk => clk_in_p,  -- only used A21 pin for clock
probe0(0) => DYNAMIC_BAUD_CLK,
probe1  => int_reg,
probe2(0) => RESET
);


It is not synthesizing and it is all because of clock.

Can you please find me a suitable free running clock and its associated pin for my PL FPGA?

Thank you
Title: Re: TE0818+TE0813
Post by: siddadd on July 25, 2025, 04:44:00 PM
I am having the same issue on the TE0817 with regards to a non-mgt free-running clock. Did you manage to resolve this issue? Which I/O pin did you use?
Title: Re: TE0818+TE0813
Post by: Antti Lukats on August 19, 2025, 04:09:01 PM
Hi,

for our modules we want to offer MOST flexibility to the user, hence we do not take one pin from FPGA fabric and connect it to clock, no we connect ALL pins to connector! This is why there is no free running clock on the fabric


There are 3 options:

option 1: the RECOMMENDED one, you boot the PS with FSBL that enable fabric clock, and you drive that clock to your FPGA fabric code. This is the way it is supposed to work. Sure this clock is not available if PS is not booted.

option 2: you feed in clock from the base-carrier board, this is also recommended way, but usually it is not needed as the PS derived clock works also

option 3: as MPSoC is UltraScale+ they still may have working STARUPE3 primitive:
https://docs.amd.com/r/en-US/ug974-vivado-ultrascale-libraries/STARTUPE3

there is CFGMCLK output that outputs some clock, this is not very accurate but could be used to feed say VIO instances

not sure if it works on MPSoC, never tried.