Trenz Electronic GmbH Support Forum

Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: batte72 on November 18, 2024, 09:33:36 AM

Title: Problem with TLK106 on TEO712 RMII mode not run
Post by: batte72 on November 18, 2024, 09:33:36 AM
 Good morning I have my udp Ip module that connect to TLK106 in RMII mode. I try to combine boostrap and BMCR bit autonegotiation in this manner:

I put High  at reset the PIN 17 and PIn 27 and after 200us I put pin17 in 'Z' and pin27  how input , then I sent with Typical MDC/MDIO Write Operation 4 sequence DEVICE_ADDR=00001  BMCR_ADDR = "00000"


    DATA_0      : std_logic_vector(15 downto 0) := "0001000000000000"; -- Dato 0
    DATA_1      : std_logic_vector(15 downto 0) := "0001001000000000"; -- Dato 1
    DATA_2      : std_logic_vector(15 downto 0) := "0001000000000000"; -- Dato 2
    DATA_3      : std_logic_vector(15 downto 0) := "0000000100000000"; -- Dato 3
    DATA_4      : std_logic_vector(15 downto 0) := "1000000000000000"; -- Dato 4

But when I send a test packet via PC the connection with ethernet in panel control is broken and TLK106 not run .I checked with ILA the clock 25MHz on MDC its ok !
Thanks




Title: Re: Problem with TLK106 on TEO712 RMII mode not run
Post by: Antti Lukats on April 24, 2025, 04:20:11 PM
sorry we can not help with custom IP cores.