Hello,
i'm using the TE0803 with a custom carrier board. Finally everything is working except the PCIe connection to the NVME SSD (M.2 card).
I'm using two lanes, the clock is coming from pins B1 and B3, just like on the TE0808.
The highspeed layout seems to be fine, I took care of length matching and impedance. Routing of highspeed signals is just as on the TE0808.
PERST is levelshifted and connected to MIO31.
On the oscilloscope i can see the clock but the linux always says PCI link DOWN.
On my m.2 connector I connected CONFIG_0, CONFIG_2, CONFIG_3 to GND.
CONFIG_1 is pulled up to 3V3.
DEVSLP is connected to GND.
PEWAKE, CLKREQ, SUSCLK is left open.
What could be the problem? I was thinking about the config/wake... pins, on the TE0808 they are going to a Port expander.
Thanks in advance
Julian
Hello,
what did you mean with
Quotethe clock is coming from pins B1 and B3, just like on the TE0808.
B1/B3 are pin coordinates from SoC or other component? TE0808 has other packages than TE0803 Soc, also PLL is other one in case you use PLL on TE0803 for PCIe CLK.
br
John
Hi John,
B1/B3 are the Pins of the TE0803. On the TE0808 these pins are routed directly to the PCI_REF pins of the PCI connector
Julian
Hi,
QuoteB1/B3 are the Pins of the TE0803.
TE0803 is a module. there are many different devices on the module. Pin coordinate B1/B3 on ZynqMP (SoC) are:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0803/REV03/Documents
B1: Bank 66 IO_L7N... see schematic page 10
B3: Bank 66 IO_L9P... see schematic page 10
QuoteOn the TE0808 these pins are routed directly to the PCI_REF pins of the PCI connector
You mean TEBF0808? PS: TE0808 is also module for TEBF0808
But when you mean the pins which goes to the PCIe connector:
PCIe clk comes from J2-1 and J2-3. --> can it be that you mean with B1/B3 these B2B connector Pins? --> but there are 4 connectors ;-)
On TE0803 it will be sources by SI5338 and ond TE0808 from SI5345. These PLLs are not programmed. this can be done by FSBL --> See Reference Design.
But GTR which are used for PCIe use other REF CLK --> this depends on your PS IP setup. We have one example online --> See Reference Design.
So at the end you must use SI53xx initialisation via FSBL and you must set correct PS IP setup.
br
John
Hi,
sorry my post was misleading. I have the TE0803 module and a TEBF0808 carrier board for testing.
So clock is coming from the SI5338... and yes I mean J2-1 and J2-2, there i can see the clock with the oscilloscope. So it seems to work.
So the configuration is the same no matter if I use the TE0803 with the TEBF0808 or my custom board ?
But with TEBF0808 it works, with my carrier not
Hi,
are all SI5338 outputs are programmed? Same frequencies link you program when you start with TEBF0808?
For PCIe are 2 CLKs needed. On which goes to the PCIe card and one which goes to the GTR refclk which is set on your PS IP.
You use also the SI programming via FSBL?
Did you use FSBL source code from starterkit or did you create your own? In case of our template, you has also an I2C mux on your board?
You select the same GTR interface for on your design like on the design which is running with the TEBF0808?
br
John