Hi all,
i am neu with te0720, ii am trying to create in vivado a microblaze which will send msg trought ethernet without use of zynq PS.
i create a block diagram Axi ethernetLitle and Ethernet PHY MII to Reduced MII problem is i didnt find the pin for the port rmii_rtl_rx_er,diff_clock_rtl_clk_p,rmii_rtl_crs_dv.
Hi,
at first PS and PL belongs together. Work with PL only is possible, but some functionality of ZYNQ depends on PS. For example boot process, PS-PL CLKs...
- https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
TE0720 ETH PHY is connected to PS. Which carrier and which ETH PHY did you use?
Did you checked this Xilinx documentation and this one from your phy?:
- https://www.xilinx.com/products/intellectual-property/axi_ethernetlite.html#overview
- https://www.xilinx.com/products/intellectual-property/reduced_media_independent_interface.html#documentation
br
John
thanks John for ur answer :)
i am using t0706-02 carrier and Marvell 88E1512.
i know that i can use PL only i already did with Zedboard but i still neu with te0720
there is my bock desing
Hi,
Marvell PHY on TE0706 has RGMII interface. You want to connect RMII to RGMII, this is not or not so easy possible as I know.
I didn't know why you want to wast PL logic with processor and periphery logic on an zynq. Use Zynq PS and route on of the ETH interface to EMIO an connect with GMII to RGMII to the second eth phy.
br
John
i need in my project that the PL has the control on ethernet .thats why i am trying to creat a connection from PL .
Do u have any suggestion please. I am thinking now to use the 1G/2.5 G Ethernet Subsystem and specify the RGMII interface
Hi,
these are all solutions from xilinx:
https://www.xilinx.com/products/technology/ethernet.html
TEMAC
https://www.xilinx.com/products/intellectual-property/temac.html#overview
or your suggested subsystem
https://www.xilinx.com/products/intellectual-property/axi_ethernet.html
but both are not free available.
br
John