diff --git a/lib/sw_apps/zynq_fsbl/src/fsbl_hooks.c b/lib/sw_apps/zynq_fsbl/src/fsbl_hooks.c index c1014e53c9..6f24826dfe 100644 --- a/lib/sw_apps/zynq_fsbl/src/fsbl_hooks.c +++ b/lib/sw_apps/zynq_fsbl/src/fsbl_hooks.c @@ -58,6 +58,10 @@ u32 FsblHookBeforeBitstreamDload(void) * and returned */ fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n"); + /* TE Mod:*/ + Status = TE_FsblHookBeforeBitstreamDload(); +/* TE Mod: finished*/ + return (Status); } @@ -85,7 +89,9 @@ u32 FsblHookAfterBitstreamDload(void) * Errors to be stored in the status variable and returned */ fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n"); - +/* TE Mod:*/ + Status = TE_FsblHookAfterBitstreamDload(); +/* TE Mod: finished*/ return (Status); } @@ -112,7 +118,9 @@ u32 FsblHookBeforeHandoff(void) * Errors to be stored in the status variable and returned */ fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n"); - +/* TE Mod:*/ + Status = TE_FsblHookBeforeHandoff(); +/* TE Mod: finished*/ return (Status); } @@ -132,6 +140,9 @@ void FsblHookFallback(void) * Errors to be stored in the status variable and returned */ fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n"); +/* TE Mod:*/ + TE_FsblHookFallback(); +/* TE Mod: finished*/ while(1); } diff --git a/lib/sw_apps/zynq_fsbl/src/fsbl_hooks.h b/lib/sw_apps/zynq_fsbl/src/fsbl_hooks.h index 9490084153..70fb4dda7d 100644 --- a/lib/sw_apps/zynq_fsbl/src/fsbl_hooks.h +++ b/lib/sw_apps/zynq_fsbl/src/fsbl_hooks.h @@ -32,6 +32,9 @@ extern "C" { /***************************** Include Files *********************************/ #include "fsbl.h" +/* TE Mod:*/ +#include "te_fsbl_hooks.h" +/* TE Mod: finished*/ /************************** Function Prototypes ******************************/ diff --git a/lib/sw_apps/zynq_fsbl/src/main.c b/lib/sw_apps/zynq_fsbl/src/main.c index 62a5b4dd64..1bf4e3c0d3 100644 --- a/lib/sw_apps/zynq_fsbl/src/main.c +++ b/lib/sw_apps/zynq_fsbl/src/main.c @@ -270,7 +270,14 @@ int main(void) fsbl_printf(DEBUG_GENERAL,"Release %d.%d %s-%s\r\n", SDK_RELEASE_YEAR, SDK_RELEASE_QUARTER, __DATE__,__TIME__); - +// TE Mod : + xil_printf("\r\n--------------------------------------------------------------------------------\r\n"); + xil_printf("Xilinx First Stage Boot Loader (TE modified) \n\r"); + xil_printf("Release %d.%d %s-%s\r\n", + SDK_RELEASE_YEAR, SDK_RELEASE_QUARTER, + __DATE__,__TIME__); + +// TE Mod finished #ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR /* diff --git a/lib/sw_apps/zynq_fsbl/src/te_Si5338-Registers.h b/lib/sw_apps/zynq_fsbl/src/te_Si5338-Registers.h new file mode 100644 index 0000000000..d70c05100b --- /dev/null +++ b/lib/sw_apps/zynq_fsbl/src/te_Si5338-Registers.h @@ -0,0 +1,438 @@ +//Register map for use with AN428 (JumpStart) +//http://www.skyworksinc.com/timing +//#BEGIN_HEADER +//Date = Monday, August 30, 2021 10:28 AM +//File version = 3 +//Software Name = ClockBuilder Pro +//Software version = 4.0.0.0 +//Software date = 7 26, 2021 +//Chip = Si533x +//Part Number = Si533x +//#END_HEADER +//Input Frequency (MHz) = 100.000000000 +//Input Type = LVDS_LVPECL_HCSL +//P1 = 4 +//Input Mux = DivRefClk +//FDBK Input Frequency (MHz) = 100.000000000 +//FDBK Input Type = OFF +//P2 = 1 +//FDBK Mux = NoClk +//PFD Input Frequency (MHz) = 25.000000000 +//VCO Frequency (GHz) = 2.600000 +//N = 104 (104.0000) +//Internal feedback enabled +//Output Clock 0 +// Output Frequency (MHz) = 100.000000000 +// Mux Selection = IDn +// MultiSynth = 26 (26.0000) +// R = 1 +//Output Clock 1 +// Output Frequency (MHz) = 50.000000000 +// Mux Selection = IDn +// MultiSynth = 52 (52.0000) +// R = 1 +//Output Clock 2 +// Output Frequency (MHz) = 100.000000000 +// Mux Selection = CLKIN +// R = 1 +//Output Clock 3 +// Output Frequency (MHz) = 50.000000000 +// Mux Selection = IDn +// MultiSynth = 52 (52.0000) +// R = 1 +//Driver 0 +// Enabled +// Powered on +// Output voltage = 1.80 +// Output type = 1.8V LVDS +// Output state when disabled = StopLow +//Driver 1 +// Enabled +// Powered on +// Output voltage = 3.30 +// Output type = 3.3V CMOS on A and B +// Output state when disabled = StopLow +//Driver 2 +// Enabled +// Powered on +// Output voltage = 1.80 +// Output type = 1.8V LVDS +// Output state when disabled = AlwaysOn +//Driver 3 +// Enabled +// Powered on +// Output voltage = 1.80 +// Output type = 1.8V LVDS +// Output state when disabled = StopLow +//Clock 0 phase inc/dec step size (ns) = 0.000 +//Clock 1 phase inc/dec step size (ns) = 0.000 +//Clock 2 phase inc/dec step size (ns) = 0.000 +//Clock 3 phase inc/dec step size (ns) = 0.000 +//Phase increment and decrement pin control is off +//Frequency increment and decrement pin control is off +//Frequency increment and decrement is disabled +//Initial phase offset 0 (ns) = 0.000 +//Initial phase offset 1 (ns) = 0.000 +//Initial phase offset 2 (ns) = 0.000 +//Initial phase offset 3 (ns) = 0.000 +//SSC is disabled + +#define NUM_REGS_MAX 350 + +typedef struct Reg_Data{ + unsigned char Reg_Addr; + unsigned char Reg_Val; + unsigned char Reg_Mask; +} Reg_Data; + +Reg_Data const Reg_Store[NUM_REGS_MAX] = { +{ 0,0x00,0x00}, +{ 1,0x00,0x00}, +{ 2,0x00,0x00}, +{ 3,0x00,0x00}, +{ 4,0x00,0x00}, +{ 5,0x00,0x00}, +{ 6,0x08,0x1D}, +{ 7,0x00,0x00}, +{ 8,0x70,0x00}, +{ 9,0x0F,0x00}, +{ 10,0x00,0x00}, +{ 11,0x00,0x00}, +{ 12,0x00,0x00}, +{ 13,0x00,0x00}, +{ 14,0x00,0x00}, +{ 15,0x00,0x00}, +{ 16,0x00,0x00}, +{ 17,0x00,0x00}, +{ 18,0x00,0x00}, +{ 19,0x00,0x00}, +{ 20,0x00,0x00}, +{ 21,0x00,0x00}, +{ 22,0x00,0x00}, +{ 23,0x00,0x00}, +{ 24,0x00,0x00}, +{ 25,0x00,0x00}, +{ 26,0x00,0x00}, +{ 27,0x70,0x80}, +{ 28,0x03,0xFF}, +{ 29,0x42,0xFF}, +{ 30,0xB0,0xFF}, +{ 31,0xC0,0xFF}, +{ 32,0xC0,0xFF}, +{ 33,0x22,0xFF}, +{ 34,0xC0,0xFF}, +{ 35,0xA2,0xFF}, +{ 36,0x06,0x1F}, +{ 37,0x03,0x1F}, +{ 38,0x06,0x1F}, +{ 39,0x06,0x1F}, +{ 40,0xE4,0xFF}, +{ 41,0x12,0x7F}, +{ 42,0x24,0x3F}, +{ 43,0x00,0x00}, +{ 44,0x00,0x00}, +{ 45,0x00,0xFF}, +{ 46,0x00,0xFF}, +{ 47,0x14,0x3F}, +{ 48,0x35,0xFF}, +{ 49,0x00,0xFF}, +{ 50,0xC3,0xFF}, +{ 51,0x07,0xFF}, +{ 52,0x10,0xFF}, +{ 53,0x00,0xFF}, +{ 54,0x0B,0xFF}, +{ 55,0x00,0xFF}, +{ 56,0x00,0xFF}, +{ 57,0x00,0xFF}, +{ 58,0x00,0xFF}, +{ 59,0x01,0xFF}, +{ 60,0x00,0xFF}, +{ 61,0x00,0xFF}, +{ 62,0x00,0x3F}, +{ 63,0x10,0xFF}, +{ 64,0x00,0xFF}, +{ 65,0x18,0xFF}, +{ 66,0x00,0xFF}, +{ 67,0x00,0xFF}, +{ 68,0x00,0xFF}, +{ 69,0x00,0xFF}, +{ 70,0x01,0xFF}, +{ 71,0x00,0xFF}, +{ 72,0x00,0xFF}, +{ 73,0x00,0x3F}, +{ 74,0x10,0xFF}, +{ 75,0x00,0xFF}, +{ 76,0x0B,0xFF}, +{ 77,0x00,0xFF}, +{ 78,0x00,0xFF}, +{ 79,0x00,0xFF}, +{ 80,0x00,0xFF}, +{ 81,0x01,0xFF}, +{ 82,0x00,0xFF}, +{ 83,0x00,0xFF}, +{ 84,0x00,0x3F}, +{ 85,0x10,0xFF}, +{ 86,0x00,0xFF}, +{ 87,0x18,0xFF}, +{ 88,0x00,0xFF}, +{ 89,0x00,0xFF}, +{ 90,0x00,0xFF}, +{ 91,0x00,0xFF}, +{ 92,0x01,0xFF}, +{ 93,0x00,0xFF}, +{ 94,0x00,0xFF}, +{ 95,0x00,0x3F}, +{ 96,0x10,0x00}, +{ 97,0x00,0xFF}, +{ 98,0x32,0xFF}, +{ 99,0x00,0xFF}, +{100,0x00,0xFF}, +{101,0x00,0xFF}, +{102,0x00,0xFF}, +{103,0x01,0xFF}, +{104,0x00,0xFF}, +{105,0x00,0xFF}, +{106,0x80,0xBF}, +{107,0x00,0xFF}, +{108,0x00,0xFF}, +{109,0x00,0xFF}, +{110,0x40,0xFF}, +{111,0x00,0xFF}, +{112,0x00,0xFF}, +{113,0x00,0xFF}, +{114,0x40,0xFF}, +{115,0x00,0xFF}, +{116,0x80,0xFF}, +{117,0x00,0xFF}, +{118,0xC0,0xFF}, +{119,0x00,0xFF}, +{120,0x00,0xFF}, +{121,0x00,0xFF}, +{122,0x40,0xFF}, +{123,0x00,0xFF}, +{124,0x00,0xFF}, +{125,0x00,0xFF}, +{126,0x00,0xFF}, +{127,0x00,0xFF}, +{128,0x00,0xFF}, +{129,0x00,0x0F}, +{130,0x00,0x0F}, +{131,0x00,0xFF}, +{132,0x00,0xFF}, +{133,0x00,0xFF}, +{134,0x00,0xFF}, +{135,0x00,0xFF}, +{136,0x00,0xFF}, +{137,0x00,0xFF}, +{138,0x00,0xFF}, +{139,0x00,0xFF}, +{140,0x00,0xFF}, +{141,0x00,0xFF}, +{142,0x00,0xFF}, +{143,0x00,0xFF}, +{144,0x00,0xFF}, +{145,0x00,0x00}, +{146,0xFF,0x00}, +{147,0x00,0x00}, +{148,0x00,0x00}, +{149,0x00,0x00}, +{150,0x00,0x00}, +{151,0x00,0x00}, +{152,0x00,0xFF}, +{153,0x00,0xFF}, +{154,0x00,0xFF}, +{155,0x00,0xFF}, +{156,0x00,0xFF}, +{157,0x00,0xFF}, +{158,0x00,0x0F}, +{159,0x00,0x0F}, +{160,0x00,0xFF}, +{161,0x00,0xFF}, +{162,0x00,0xFF}, +{163,0x00,0xFF}, +{164,0x00,0xFF}, +{165,0x00,0xFF}, +{166,0x00,0xFF}, +{167,0x00,0xFF}, +{168,0x00,0xFF}, +{169,0x00,0xFF}, +{170,0x00,0xFF}, +{171,0x00,0xFF}, +{172,0x00,0xFF}, +{173,0x00,0xFF}, +{174,0x00,0xFF}, +{175,0x00,0xFF}, +{176,0x00,0xFF}, +{177,0x00,0xFF}, +{178,0x00,0xFF}, +{179,0x00,0xFF}, +{180,0x00,0xFF}, +{181,0x00,0x0F}, +{182,0x00,0xFF}, +{183,0x00,0xFF}, +{184,0x00,0xFF}, +{185,0x00,0xFF}, +{186,0x00,0xFF}, +{187,0x00,0xFF}, +{188,0x00,0xFF}, +{189,0x00,0xFF}, +{190,0x00,0xFF}, +{191,0x00,0xFF}, +{192,0x00,0xFF}, +{193,0x00,0xFF}, +{194,0x00,0xFF}, +{195,0x00,0xFF}, +{196,0x00,0xFF}, +{197,0x00,0xFF}, +{198,0x00,0xFF}, +{199,0x00,0xFF}, +{200,0x00,0xFF}, +{201,0x00,0xFF}, +{202,0x00,0xFF}, +{203,0x00,0x0F}, +{204,0x00,0xFF}, +{205,0x00,0xFF}, +{206,0x00,0xFF}, +{207,0x00,0xFF}, +{208,0x00,0xFF}, +{209,0x00,0xFF}, +{210,0x00,0xFF}, +{211,0x00,0xFF}, +{212,0x00,0xFF}, +{213,0x00,0xFF}, +{214,0x00,0xFF}, +{215,0x00,0xFF}, +{216,0x00,0xFF}, +{217,0x00,0xFF}, +{218,0x00,0x00}, +{219,0x00,0x00}, +{220,0x00,0x00}, +{221,0x0D,0x00}, +{222,0x00,0x00}, +{223,0x00,0x00}, +{224,0xF4,0x00}, +{225,0xF0,0x00}, +{226,0x00,0x00}, +{227,0x00,0x00}, +{228,0x00,0x00}, +{229,0x00,0x00}, +{231,0x00,0x00}, +{232,0x00,0x00}, +{233,0x00,0x00}, +{234,0x00,0x00}, +{235,0x00,0x00}, +{236,0x00,0x00}, +{237,0x00,0x00}, +{238,0x14,0x00}, +{239,0x00,0x00}, +{240,0x00,0x00}, +{242,0x02,0x02}, +{243,0xF0,0x00}, +{244,0x00,0x00}, +{245,0x00,0x00}, +{247,0x00,0x00}, +{248,0x00,0x00}, +{249,0xA8,0x00}, +{250,0x00,0x00}, +{251,0x84,0x00}, +{252,0x00,0x00}, +{253,0x00,0x00}, +{254,0x00,0x00}, +{255, 1, 0xFF}, // set page bit to 1 +{ 0,0x00,0x00}, +{ 1,0x00,0x00}, +{ 2,0x00,0x00}, +{ 3,0x00,0x00}, +{ 4,0x00,0x00}, +{ 5,0x00,0x00}, +{ 6,0x00,0x00}, +{ 7,0x00,0x00}, +{ 8,0x00,0x00}, +{ 9,0x00,0x00}, +{ 10,0x00,0x00}, +{ 11,0x00,0x00}, +{ 12,0x00,0x00}, +{ 13,0x00,0x00}, +{ 14,0x00,0x00}, +{ 15,0x00,0x00}, +{ 16,0x00,0x00}, +{ 17,0x01,0x00}, +{ 18,0x00,0x00}, +{ 19,0x00,0x00}, +{ 20,0x90,0x00}, +{ 21,0x31,0x00}, +{ 22,0x00,0x00}, +{ 23,0x00,0x00}, +{ 24,0x01,0x00}, +{ 25,0x00,0x00}, +{ 26,0x00,0x00}, +{ 27,0x00,0x00}, +{ 28,0x00,0x00}, +{ 29,0x00,0x00}, +{ 30,0x00,0x00}, +{ 31,0x00,0xFF}, +{ 32,0x00,0xFF}, +{ 33,0x01,0xFF}, +{ 34,0x00,0xFF}, +{ 35,0x00,0xFF}, +{ 36,0x90,0xFF}, +{ 37,0x31,0xFF}, +{ 38,0x00,0xFF}, +{ 39,0x00,0xFF}, +{ 40,0x01,0xFF}, +{ 41,0x00,0xFF}, +{ 42,0x00,0xFF}, +{ 43,0x00,0x0F}, +{ 44,0x00,0x00}, +{ 45,0x00,0x00}, +{ 46,0x00,0x00}, +{ 47,0x00,0xFF}, +{ 48,0x00,0xFF}, +{ 49,0x01,0xFF}, +{ 50,0x00,0xFF}, +{ 51,0x00,0xFF}, +{ 52,0x90,0xFF}, +{ 53,0x31,0xFF}, +{ 54,0x00,0xFF}, +{ 55,0x00,0xFF}, +{ 56,0x01,0xFF}, +{ 57,0x00,0xFF}, +{ 58,0x00,0xFF}, +{ 59,0x00,0x0F}, +{ 60,0x00,0x00}, +{ 61,0x00,0x00}, +{ 62,0x00,0x00}, +{ 63,0x00,0xFF}, +{ 64,0x00,0xFF}, +{ 65,0x01,0xFF}, +{ 66,0x00,0xFF}, +{ 67,0x00,0xFF}, +{ 68,0x90,0xFF}, +{ 69,0x31,0xFF}, +{ 70,0x00,0xFF}, +{ 71,0x00,0xFF}, +{ 72,0x01,0xFF}, +{ 73,0x00,0xFF}, +{ 74,0x00,0xFF}, +{ 75,0x00,0x0F}, +{ 76,0x00,0x00}, +{ 77,0x00,0x00}, +{ 78,0x00,0x00}, +{ 79,0x00,0xFF}, +{ 80,0x00,0xFF}, +{ 81,0x00,0xFF}, +{ 82,0x00,0xFF}, +{ 83,0x00,0xFF}, +{ 84,0x90,0xFF}, +{ 85,0x31,0xFF}, +{ 86,0x00,0xFF}, +{ 87,0x00,0xFF}, +{ 88,0x01,0xFF}, +{ 89,0x00,0xFF}, +{ 90,0x00,0xFF}, +{ 91,0x00,0x0F}, +{ 92,0x00,0x00}, +{ 93,0x00,0x00}, +{ 94,0x00,0x00}, +{255, 0, 0xFF} }; // set page bit to 0 +//End of file diff --git a/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks.c b/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks.c new file mode 100644 index 0000000000..905ce54c8a --- /dev/null +++ b/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks.c @@ -0,0 +1,353 @@ +/****************************************************************************** +* +* +* +******************************************************************************/ + +/***************************************************************************** +* +* @file te_fsbl_hooks.c +* +* +******************************************************************************/ + + +#include "fsbl.h" +#include "xstatus.h" +#include "te_fsbl_hooks.h" +#include "xparameters.h" + +/************************** Variable Definitions *****************************/ +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are only defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID + +/** + * @name Configuration Type1 packet headers masks + * @{ + */ +#define XDC_TYPE_SHIFT 29 +#define XDC_REGISTER_SHIFT 13 +#define XDC_OP_SHIFT 27 +#define XDC_TYPE_1 1 +#define OPCODE_READ 1 +/* @} */ + +/* + * Addresses of the Configuration Registers + */ +#define CRC 0 /* Status Register */ +#define FAR 1 /* Frame Address Register */ +#define FDRI 2 /* FDRI Register */ +#define FDRO 3 /* FDRO Register */ +#define CMD 4 /* Command Register */ +#define CTL0 5 /* Control Register 0 */ +#define MASK 6 /* MASK Register */ +#define STAT 7 /* Status Register */ +#define LOUT 8 /* LOUT Register */ +#define COR0 9 /* Configuration Options Register 0 */ +#define MFWR 10 /* MFWR Register */ +#define CBC 11 /* CBC Register */ +#define IDCODE 12 /* IDCODE Register */ +#define AXSS 13 /* AXSS Register */ +#define COR1 14 /* Configuration Options Register 1 */ +#define WBSTAR 15 /* Warm Boot Start Address Register */ +#define TIMER 16 /* Watchdog Timer Register */ +#define BOOTSTS 17 /* Boot History Status Register */ +#define CTL1 18 /* Control Register 1 */ + +/************************** Function Prototypes ******************************/ + +XDcfg DcfgInstance; /* Device Configuration Interface Instance */ +/*****************************************************************************/ + +/* + * read IDCODE over PCAP + * + */ + +u32 XDcfg_RegAddr(u8 Register, u8 OpCode, u8 Size) +{ + /* + * Type 1 Packet Header Format + * The header section is always a 32-bit word. + * + * HeaderType | Opcode | Register Address | Reserved | Word Count + * [31:29] [28:27] [26:13] [12:11] [10:0] + * -------------------------------------------------------------- + * 001 xx RRRRRRRRRxxxxx RR xxxxxxxxxxx + * + * �R� means the bit is not used and reserved for future use. + * The reserved bits should be written as 0s. + * + * Generating the Type 1 packet header which involves sifting of Type 1 + * Header Mask, Register value and the OpCode which is 01 in this case + * as only read operation is to be carried out and then performing OR + * operation with the Word Length. + */ + return ( ((XDC_TYPE_1 << XDC_TYPE_SHIFT) | + (Register << XDC_REGISTER_SHIFT) | + (OpCode << XDC_OP_SHIFT)) | Size); +} + + +int XDcfg_GetConfigReg(XDcfg *DcfgInstancePtr, u32 ConfigReg, u32 *RegData) +{ + u32 IntrStsReg; + u32 StatusReg; + unsigned int CmdIndex; + unsigned int CmdBuf[18]; + + /* + * Clear the interrupt status bits + */ + XDcfg_IntrClear(DcfgInstancePtr, (XDCFG_IXR_PCFG_DONE_MASK | + XDCFG_IXR_D_P_DONE_MASK | XDCFG_IXR_DMA_DONE_MASK)); + + /* Check if DMA command queue is full */ + StatusReg = XDcfg_ReadReg(DcfgInstancePtr->Config.BaseAddr, + XDCFG_STATUS_OFFSET); + if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == + XDCFG_STATUS_DMA_CMD_Q_F_MASK) { + return XST_FAILURE; + } + + /* + * Register Readback in non secure mode + * Create the data to be written to read back the + * Configuration Registers from PL Region. + */ + CmdIndex = 0; + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0x000000BB; /* Bus Width Sync Word */ + CmdBuf[CmdIndex++] = 0x11220044; /* Bus Width Detect */ + CmdBuf[CmdIndex++] = 0xFFFFFFFF; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0xAA995566; /* Sync Word */ + CmdBuf[CmdIndex++] = 0x20000000; /* Type 1 NOOP Word 0 */ + CmdBuf[CmdIndex++] = XDcfg_RegAddr(ConfigReg,OPCODE_READ,0x1); + CmdBuf[CmdIndex++] = 0x20000000; /* Type 1 NOOP Word 0 */ + CmdBuf[CmdIndex++] = 0x20000000; /* Type 1 NOOP Word 0 */ + + XDcfg_Transfer(&DcfgInstance, (&CmdBuf[0]), + CmdIndex, RegData, 1, XDCFG_PCAP_READBACK); + + /* Poll IXR_DMA_DONE */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + while ((IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) != + XDCFG_IXR_DMA_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + } + + /* Poll IXR_D_P_DONE */ + while ((IntrStsReg & XDCFG_IXR_D_P_DONE_MASK) != + XDCFG_IXR_D_P_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + } + + CmdIndex = 0; + CmdBuf[CmdIndex++] = 0x30008001; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0x0000000D; /* Bus Width Sync Word */ + CmdBuf[CmdIndex++] = 0x20000000; /* Bus Width Detect */ + CmdBuf[CmdIndex++] = 0x20000000; /* Dummy Word */ + CmdBuf[CmdIndex++] = 0x20000000; /* Bus Width Detect */ + CmdBuf[CmdIndex++] = 0x20000000; /* Dummy Word */ + + XDcfg_InitiateDma(DcfgInstancePtr, (u32)(&CmdBuf[0]), + XDCFG_DMA_INVALID_ADDRESS, CmdIndex, 0); + + /* Poll IXR_DMA_DONE */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + while ((IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) != + XDCFG_IXR_DMA_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + } + + /* Poll IXR_D_P_DONE */ + while ((IntrStsReg & XDCFG_IXR_D_P_DONE_MASK) != + XDCFG_IXR_D_P_DONE_MASK) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstancePtr); + } + + return XST_SUCCESS; +} + +u32 te_read_IDCODE(void) +{ + int Status; + unsigned int ValueBack; + unsigned int tmval; + XDcfg_Config *ConfigPtr; + + /* + * Initialize the Device Configuration Interface driver. + */ + ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID); + + /* + * This is where the virtual address would be used, this example + * uses physical address. + */ + Status = XDcfg_CfgInitialize(&DcfgInstance, ConfigPtr, + ConfigPtr->BaseAddr); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Run the Self test. + */ + Status = XDcfg_SelfTest(&DcfgInstance); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + + if (XDcfg_GetConfigReg(&DcfgInstance, IDCODE, (u32 *)&ValueBack) != + XST_SUCCESS) { + return XST_FAILURE; + } + + xil_printf("\r\nDevice IDCODE: %x", ValueBack ); + tmval=(ValueBack & 0x0001F000)>>12; + xil_printf("\r\nDevice Name: "); + if (tmval==0x08) { xil_printf("7z014s");} + else if (tmval==0x03) { xil_printf("7z007s");} + else if (tmval==0x02) { xil_printf("7z010");} + else if (tmval==0x1b) { xil_printf("7z015");} + else if (tmval==0x07) { xil_printf("7z020");} + else if (tmval==0x0c) { xil_printf("7z030");} + else if (tmval==0x11) { xil_printf("7z045");} + else { xil_printf("(...)", tmval);} + xil_printf(" (%x)", tmval); + tmval=(ValueBack & 0xF0000000)>>28; + xil_printf("\r\nDevice Revision: %x ", tmval); + return XST_SUCCESS; +} +/****************************************************************************** +* This function is the hook which will be called before the bitstream download. +* The user can add all the customized code required to be executed before the +* bitstream download to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 TE_FsblHookBeforeBitstreamDload(void) +{ + u32 Status; + + Status = XST_SUCCESS; + + /* + * User logic to be added here. Errors to be stored in the status variable + * and returned + */ + fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n"); + + #if defined(ENABLE_TE_HOOKS_BD) + Status = TE_FsblHookBeforeBitstreamDload_Custom(); + #endif + + return (Status); +} + +/****************************************************************************** +* This function is the hook which will be called after the bitstream download. +* The user can add all the customized code required to be executed after the +* bitstream download to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 TE_FsblHookAfterBitstreamDload(void) +{ + u32 Status; + + Status = XST_SUCCESS; + + /* + * User logic to be added here. + * Errors to be stored in the status variable and returned + */ + fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n"); + #if defined(ENABLE_TE_HOOKS_AD) + Status = TE_FsblHookAfterBitstreamDload_Custom(); + #endif + + return (Status); +} + +/****************************************************************************** +* This function is the hook which will be called before the FSBL does a handoff +* to the application. The user can add all the customized code required to be +* executed before the handoff to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 TE_FsblHookBeforeHandoff(void) +{ + u32 Status; + + Status = XST_SUCCESS; + + /* + * User logic to be added here. + * Errors to be stored in the status variable and returned + */ + fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n"); + + Status = te_read_IDCODE(); // general include to display Device ID of the zynq + #if defined(ENABLE_TE_HOOKS_BH) + Status = TE_FsblHookBeforeHandoff_Custom(); + #endif + + return (Status); +} + + +/****************************************************************************** +* This function is the hook which will be called in case FSBL fall back +* +* @param None +* +* @return None +* +****************************************************************************/ +void TE_FsblHookFallback(void) +{ + /* + * User logic to be added here. + * Errors to be stored in the status variable and returned + */ + fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n"); + + #if defined(ENABLE_TE_HOOKS_FB) + TE_FsblHookFallback_Custom(); + #endif + + while(1); +} + + diff --git a/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks.h b/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks.h new file mode 100644 index 0000000000..19dcbaec68 --- /dev/null +++ b/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* +* +* +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file te_fsbl_hooks.h +* +******************************************************************************/ +#ifndef TE_FSBL_HOOKS_H_ +#define TE_FSBL_HOOKS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "fsbl.h" +// rename and enable custom TE hooks +// #include "te_fsbl_hooks_te0720.h" +#include "te_fsbl_hooks_te0715.h" +// #define ENABLE_TE_HOOKS_BD //TE_FsblHookBeforeBitstreamDload +// #define ENABLE_TE_HOOKS_AD //TE_FsblHookAfterBitstreamDload +#define ENABLE_TE_HOOKS_BH //TE_FsblHookBeforeHandoff +// #define ENABLE_TE_HOOKS_FB //TE_FsblHookFallback + +/************************** Function Prototypes ******************************/ + +/* FSBL hook function which is called before bitstream download */ +u32 TE_FsblHookBeforeBitstreamDload(void); + +/* FSBL hook function which is called after bitstream download */ +u32 TE_FsblHookAfterBitstreamDload(void); + +/* FSBL hook function which is called before handoff to the application */ +u32 TE_FsblHookBeforeHandoff(void); + +/* FSBL hook function which is called in FSBL fallback */ +void TE_FsblHookFallback(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks_te0715.c b/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks_te0715.c new file mode 100644 index 0000000000..e80b350a33 --- /dev/null +++ b/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks_te0715.c @@ -0,0 +1,139 @@ +/****************************************************************************** +* +* +* +* +******************************************************************************/ + +/***************************************************************************** +* +* @file te_fsbl_hooks.c +* +* +******************************************************************************/ + + +#include "fsbl.h" +#include "xstatus.h" +//rename to correct board name +#include "te_fsbl_hooks_te0715.h" +#include "te_iic_platform.h" +#include "te_si5338.h" + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + + +/****************************************************************************** +* This function is the hook which will be called before the bitstream download. +* The user can add all the customized code required to be executed before the +* bitstream download to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 TE_FsblHookBeforeBitstreamDload_Custom(void) +{ + u32 Status; + + Status = XST_SUCCESS; + + xil_printf("\r\n--------------------------------------------------------------------------------\r\n"); + xil_printf("TE0715 TE_FsblHookBeforeBitstreamDload_Custom\r\n"); + /* Add the code here */ + xil_printf("\r\n--------------------------------------------------------------------------------\r\n"); + + + return (Status); +} + +/****************************************************************************** +* This function is the hook which will be called after the bitstream download. +* The user can add all the customized code required to be executed after the +* bitstream download to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 TE_FsblHookAfterBitstreamDload_Custom(void) +{ + u32 Status; + + Status = XST_SUCCESS; + + xil_printf("\r\n--------------------------------------------------------------------------------\r\n"); + xil_printf("TE0715 TE_FsblHookAfterBitstreamDload_Custom\r\n"); + /* Add the code here */ + xil_printf("\r\n--------------------------------------------------------------------------------\r\n"); + + return (Status); +} + +/****************************************************************************** +* This function is the hook which will be called before the FSBL does a handoff +* to the application. The user can add all the customized code required to be +* executed before the handoff to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 TE_FsblHookBeforeHandoff_Custom(void) +{ + u32 Status; + + Status = XST_SUCCESS; + + xil_printf("\r\n--------------------------------------------------------------------------------\r\n"); + xil_printf("TE0715 TE_FsblHookBeforeHandoff_Custom\r\n"); + /* Add the code here */ +#if defined(RECONFIGURE_SI5338) + Status = iic_init(); // Configure I2C Bus 0 driver instance + if (Status != XST_SUCCESS) { + xil_printf("Error:I2C Init\r\n"); + goto END; + } + xil_printf("Configure TE715 SI5338\r\n"); + Status = si5338_init(0x70); // Configure clocks + if (Status != XST_SUCCESS) { + xil_printf("Error: Configure Si5338 CLK\r\n"); + goto END; + } +#endif + xil_printf("\r\n--------------------------------------------------------------------------------\r\n"); + END: + return (Status); +} + + +/****************************************************************************** +* This function is the hook which will be called in case FSBL fall back +* +* @param None +* +* @return None +* +****************************************************************************/ +void TE_FsblHookFallback_Custom(void) +{ + + xil_printf("\r\n--------------------------------------------------------------------------------\r\n"); + xil_printf("TE0715 TE_FsblHookFallback_Custom\r\n"); + /* Add the code here */ + xil_printf("\r\n--------------------------------------------------------------------------------\r\n"); + + + //while(1); +} + + diff --git a/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks_te0715.h b/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks_te0715.h new file mode 100644 index 0000000000..78c5f6ef15 --- /dev/null +++ b/lib/sw_apps/zynq_fsbl/src/te_fsbl_hooks_te0715.h @@ -0,0 +1,46 @@ +/****************************************************************************** +* +* +* +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file te_fsbl_hooks.h +* +* +******************************************************************************/ +//rename to correct board name +#ifndef TE_FSBL_HOOKS_CUSTOM_H_ +#define TE_FSBL_HOOKS_CUSTOM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "fsbl.h" + +// Add defined to enable SI5338 reconfiguration +#define RECONFIGURE_SI5338 + +/************************** Function Prototypes ******************************/ + +/* FSBL hook function which is called before bitstream download */ +u32 TE_FsblHookBeforeBitstreamDload_Custom(void); + +/* FSBL hook function which is called after bitstream download */ +u32 TE_FsblHookAfterBitstreamDload_Custom(void); + +/* FSBL hook function which is called before handoff to the application */ +u32 TE_FsblHookBeforeHandoff_Custom(void); + +/* FSBL hook function which is called in FSBL fallback */ +void TE_FsblHookFallback_Custom(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/lib/sw_apps/zynq_fsbl/src/te_iic_define_te0715.h b/lib/sw_apps/zynq_fsbl/src/te_iic_define_te0715.h new file mode 100644 index 0000000000..391d60d344 --- /dev/null +++ b/lib/sw_apps/zynq_fsbl/src/te_iic_define_te0715.h @@ -0,0 +1,69 @@ +/* +-- Company: Trenz Electronic +-- Engineer: Oleksandr Kiyenko / John Hartfiel + */ + +#ifndef SRC_TE_IIC_DEFINE_H_ +#define SRC_TE_IIC_DEFINE_H_ + +/* Board specific settings - General example*/ + +/* use own 'main' function */ +#define TE_STANDALONE + +/* Define clock chip */ +// #define CLOCK_SI5345 +// #define NVM_CODE /* for SI5345: NVM writing is limited!, you do it on your own risk!*/ + +#define CLOCK_SI5338 + + +/* IIC interface type definition (use one that pass) */ +// #define IIC_TYPE_AXI_IIC +// #define IIC_BASE_ADDRESS XPAR_IIC_0_BASEADDR + +#define IIC_TYPE_ZYNQPS_IIC +#define XIICPS_DEVICE_ID XPAR_XIICPS_0_DEVICE_ID + +//#define IIC_TYPE_ZYNQUPS_IIC +//#define XIICPS_DEVICE_ID XPAR_XIICPS_0_DEVICE_ID + +//#define IIC_TYPE_MCS_GPIO_IIC +//#define GPIO_SDA_PIN 0 +//#define GPIO_SCL_PIN 1 + +//#define IIC_TYPE_AXI_GPIO_IIC +//#define GPIO_DEVICE_ID XPAR_GPIO_0_DEVICE_ID +//#define GPIO_CHANNEL 0 +//#define GPIO_SDA_PIN 0 +//#define GPIO_SCL_PIN 1 + +//#define IIC_TYPE_PS_GPIO_IIC +//#define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID +//#define GPIO_SDA_PIN 0 +//#define GPIO_SCL_PIN 1 + +/* Define IIC clock speed */ +#define IIC_SCLK_RATE 400000 + + +/* UART interface type definition (use one that pass) */ + +// #define UART_TYPE_AXI_UARTLITE +// #define UART_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID + +//#define UART_TYPE_AXI_UART16550 +//#define UART_DEVICE_ID XPAR_UARTNS550_0_DEVICE_ID + +#define UART_TYPE_ZYNQPS_UART +#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID + +//#define UART_TYPE_ZYNQUPS_UART +//#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID + +//#define UART_TYPE_NO_UART + +/* Define UART baudrate */ +#define UART_BAUDRATE 115200 + +#endif /* SRC_TE_IIC_DEFINE_H_ */ diff --git a/lib/sw_apps/zynq_fsbl/src/te_iic_platform.c b/lib/sw_apps/zynq_fsbl/src/te_iic_platform.c new file mode 100644 index 0000000000..dfbd0fa7a8 --- /dev/null +++ b/lib/sw_apps/zynq_fsbl/src/te_iic_platform.c @@ -0,0 +1,512 @@ +/* +-- Company: Trenz Electronic +-- Engineer: Oleksandr Kiyenko / John Hartfiel + */ +#include "te_iic_platform.h" +#include "te_uart.h" + +/*----------------------------------------------------------------------------*/ +#ifdef IIC_TYPE_AXI_IIC +int iic_init(void) +{ + int Status; + u32 StatusReg; + + /* Initialize the IIC Core. */ + Status = XIic_DynInit(IIC_BASE_ADDRESS); + if (Status != XST_SUCCESS) { + p_printf(("IIC Controller Init failure\r\n")); + return XST_FAILURE; + } + /* Make sure all the Fifo's are cleared and Bus is Not busy. */ + while (((StatusReg = XIic_ReadReg(IIC_BASE_ADDRESS, + XIIC_SR_REG_OFFSET)) & + (XIIC_SR_RX_FIFO_EMPTY_MASK | + XIIC_SR_TX_FIFO_EMPTY_MASK | + XIIC_SR_BUS_BUSY_MASK)) != + (XIIC_SR_RX_FIFO_EMPTY_MASK | + XIIC_SR_TX_FIFO_EMPTY_MASK)) { + } + return Status; +} + +int iic_write8(unsigned char chip_addr, unsigned char reg_addr, unsigned char reg_val) +{ + int Status; + u8 SentByteCount; + u8 WriteBuffer[2]; + + WriteBuffer[0] = (u8) (reg_addr); + WriteBuffer[1] = (u8) (reg_val); + Status = XST_SUCCESS; + + SentByteCount = XIic_DynSend(IIC_BASE_ADDRESS, chip_addr, WriteBuffer, 2, XIIC_STOP); + + if(SentByteCount != 2){ // All bits + Status = XST_FAILURE; + } + return Status; +} + +int iic_read8(unsigned char chip_addr, unsigned char reg_addr, unsigned char *reg_val) +{ + u8 SentByteCount; + u8 ReceivedByteCount; + u8 WriteBuffer = reg_addr; + + #ifdef DEBUG_MSG + p_printf(("iic_read8: addr 0x%04x\r\n", reg_addr)); + #endif + SentByteCount = XIic_DynSend(IIC_BASE_ADDRESS, chip_addr, &WriteBuffer, 1, XIIC_STOP); + if(SentByteCount != 1){ + return XST_FAILURE; + } + ReceivedByteCount = XIic_DynRecv(IIC_BASE_ADDRESS, chip_addr, reg_val, 1); + #ifdef DEBUG_MSG + p_printf(("iic_read8: received %d bytes = 0x%02x\r\n", ReceivedByteCount, reg_val[0])); + #endif + if(ReceivedByteCount != 1){ + return XST_FAILURE; + } + return XST_SUCCESS; +} + +void iic_delay(int delay_ms){ + volatile int i; + for(i=0;i<(delay_ms*1000000);i++); +} + +#endif /* IIC_TYPE_AXI_IIC */ + +/*----------------------------------------------------------------------------*/ +#if defined(IIC_TYPE_ZYNQPS_IIC) || defined(IIC_TYPE_ZYNQUPS_IIC) +int iic_init(void) +{ + XIicPs_Config *I2cCfgPtr; + int Status = XST_SUCCESS; + + I2cCfgPtr = XIicPs_LookupConfig(XIICPS_DEVICE_ID); + + if (I2cCfgPtr == NULL){ + p_printf(("IIC Controller lookup failure\r\n")); + return XST_FAILURE; + } + + Status = XIicPs_CfgInitialize(&I2cInstancePtr, I2cCfgPtr, I2cCfgPtr->BaseAddress); + if (Status != XST_SUCCESS) { + p_printf(("IIC Controller Init failure\r\n")); + return XST_FAILURE; + } + + XIicPs_SetSClk(&I2cInstancePtr, IIC_SCLK_RATE); + return Status; +} + +int iic_write8(unsigned char chip_addr, unsigned char reg_addr, unsigned char reg_val) +{ + u8 WriteBuffer[10]; + int Status; + + WriteBuffer[0] = reg_addr; + WriteBuffer[1] = reg_val; + Status = XIicPs_MasterSendPolled(&I2cInstancePtr, WriteBuffer, 2, chip_addr); + if (Status != XST_SUCCESS) { + return Status; + } + + // Wait until bus is idle to start another transfer + while (XIicPs_BusIsBusy(&I2cInstancePtr)) {}; + + return XST_SUCCESS; +} + +int iic_read8(unsigned char chip_addr, unsigned char reg_addr, unsigned char *data) +{ + u8 wr_data; + wr_data = reg_addr; + XIicPs_MasterSendPolled(&I2cInstancePtr, &wr_data, 1, chip_addr); + XIicPs_MasterRecvPolled(&I2cInstancePtr, data, 1, chip_addr); + while (XIicPs_BusIsBusy(&I2cInstancePtr)); + return 0; +} + +void iic_delay(int delay_ms){ + usleep(delay_ms*1000); +} + +#endif /* IIC_TYPE_ZYNQPS_IIC IIC_TYPE_ZYNQUPS_IIC */ + +/*----------------------------------------------------------------------------*/ +#ifdef IIC_TYPE_MCS_GPIO_IIC + + +void gpio_set_pin(unsigned int pin, unsigned int value) +{ + static unsigned int gpio_shadow = 0; + if(value == 0) + { + gpio_shadow &= ~(1 << pin); + } + else + { + gpio_shadow |= (1 << pin); + } + XIo_Out32(GPIO_OUT_REG, gpio_shadow); +} + +u8 gpio_get_pin(unsigned int pin) +{ + if((XIo_In32(GPIO_IN_REG) & (1 << pin)) != 0) + { + return 1; + } + return 0; +} + +int iic_init(void) +{ + gpio_set_pin(GPIO_SDA_PIN, 1); + gpio_set_pin(GPIO_SCL_PIN, 1); + return 0; +} + +#endif /* IIC_TYPE_MCS_GPIO_IIC */ + +/*----------------------------------------------------------------------------*/ +#ifdef IIC_TYPE_AXI_GPIO_IIC +int iic_init(void) +{ + int Status; + u32 dir; + Status = XGpio_Initialize(&Gpio, GPIO_DEVICE_ID); + // SCL and SDA should have PULL UP + dir = XGpio_GetDataDirection(&Gpio, GPIO_CHANNEL); + dir |= (GPIO_SDA_PIN | GPIO_SCL_PIN); + // Set Direction to IN + XGpio_SetDataDirection(&Gpio, GPIO_CHANNEL, dir); + // Set Values to 0 + XGpio_DiscreteClear(&Gpio, GPIO_CHANNEL, GPIO_SDA_PIN); + XGpio_DiscreteClear(&Gpio, GPIO_CHANNEL, GPIO_SCL_PIN); + + return Status; +} + +void gpio_set_pin(unsigned int pin, unsigned int value) +{ + u32 dir; + dir = XGpio_GetDataDirection(&Gpio, GPIO_CHANNEL); + if(value == 0){ // Set direction to OUT + dir &= ~value; + XGpio_SetDataDirection(&Gpio, GPIO_CHANNEL, dir); + } + else{ // Set direction to IN + dir |= value; + XGpio_SetDataDirection(&Gpio, GPIO_CHANNEL, dir); + } +} + +u8 gpio_get_pin(unsigned int pin) +{ + if(XGpio_DiscreteRead(&Gpio, GPIO_CHANNEL) | pin){ + return 1; + } + else{ + return 0; + } +} + +#endif /* IIC_TYPE_AXI_GPIO_IIC */ + +/*----------------------------------------------------------------------------*/ +#ifdef IIC_TYPE_PS_GPIO_IIC + +int iic_init(void) +{ + int Status; + XGpioPs_Config *ConfigPtr; + + ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID); + Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr); + // Set Direction to IN + XGpioPs_SetDirectionPin(&Gpio, GPIO_SDA_PIN, 0); + XGpioPs_SetDirectionPin(&Gpio, GPIO_SCL_PIN, 0); + // Output disable + XGpioPs_SetOutputEnablePin(&Gpio, GPIO_SDA_PIN, 0); + XGpioPs_SetOutputEnablePin(&Gpio, GPIO_SCL_PIN, 0); + // Set Values to 0 + XGpioPs_WritePin(&Gpio, GPIO_SDA_PIN, 0); + XGpioPs_WritePin(&Gpio, GPIO_SCL_PIN, 0); + + return Status; +} + +void gpio_set_pin(unsigned int pin, unsigned int value) +{ + if(value == 0){ // Set direction to OUT + // Set Direction to IN + XGpioPs_SetDirectionPin(&Gpio, value, 1); + // Output enable + XGpioPs_SetOutputEnablePin(&Gpio, value, 1); + } + else{ // Set direction to IN + // Set Direction to IN + XGpioPs_SetDirectionPin(&Gpio, value, 0); + // Output disable + XGpioPs_SetOutputEnablePin(&Gpio, value, 0); + } +} + +u8 gpio_get_pin(unsigned int pin) +{ + if(XGpioPs_ReadPin(&Gpio, Output_Pin) | pin) + { + return 1; + } + else{ + return 0; + } +} + +#endif /* IIC_TYPE_PS_GPIO_IIC */ + +/*----------------------------------------------------------------------------*/ +/* Common functions for all GPIOs implementation */ +#if defined(IIC_TYPE_MCS_GPIO_IIC) || defined(IIC_TYPE_AXI_GPIO_IIC) || defined(IIC_TYPE_PS_GPIO_IIC) + +void iic_dly(){ + volatile int i; + for(i=0;i<(1000);i++){ + } +} + +void iic_delay(int delay_ms){ + volatile int i; + for(i=0;i<(delay_ms*1000000);i++); +} + +void iic_start(void) +{ + gpio_set_pin(GPIO_SDA_PIN, 1); // Pull SDA High + gpio_set_pin(GPIO_SCL_PIN, 1); // Pull SCL High + gpio_set_pin(GPIO_SDA_PIN, 0); // pull SDA low + iic_dly(); + gpio_set_pin(GPIO_SCL_PIN, 0); // pull SCL low + iic_dly(); +} + +void iic_stop(void) +{ + gpio_set_pin(GPIO_SDA_PIN, 0); // Pull SDA low + gpio_set_pin(GPIO_SCL_PIN, 0); // Ensure SCL low + iic_dly(); + gpio_set_pin(GPIO_SCL_PIN, 1); // Pull SCL High + iic_dly(); + gpio_set_pin(GPIO_SDA_PIN, 1); // Pull SDA High + iic_dly(); + gpio_set_pin(GPIO_SCL_PIN, 0); // Pull SCL low + iic_dly(); +} + +void iic_send_bit(u8 value) +{ + gpio_set_pin(GPIO_SCL_PIN, 0); // Ensure that SCL is low + gpio_set_pin(GPIO_SDA_PIN, value); // Set data + iic_dly(); + gpio_set_pin(GPIO_SCL_PIN, 1); // Pull SCL High + iic_dly(); + gpio_set_pin(GPIO_SCL_PIN, 0); // Pull SCL low +} + +u8 iic_receive_bit() +{ + u8 rcv_data; + + gpio_set_pin(GPIO_SCL_PIN, 0); // Ensure that SCL is low + gpio_set_pin(GPIO_SDA_PIN, 1); // Pull SDA High + iic_dly(); + gpio_set_pin(GPIO_SCL_PIN, 1); // Pull SCL High + iic_dly(); + rcv_data = gpio_get_pin(GPIO_SDA_PIN); + gpio_set_pin(GPIO_SCL_PIN, 0); // Pull SCL low + return rcv_data; +} + +u8 iic_write(u8 value) +{ + u8 i; + u8 shifter = value; + + for(i = 0; i < 8; i++) + { + iic_send_bit(shifter >> 7); + shifter = shifter << 1; + } + return iic_receive_bit(); +} + +u8 iic_read(u8 ack) +{ + u8 i, shifter; + + for (i = 0; i < 8; i++) // loop through each bit + { + shifter = shifter << 1; + shifter |= iic_receive_bit(); + } + iic_send_bit(ack); // Send ACK/NACK + return shifter; +} + +int iic_write8(unsigned char chip_addr, unsigned char reg_addr, unsigned char reg_val) +{ + int Status = 0; + + iic_start(); + Status = iic_write(chip_addr << 1); // Chip addr & Write + if(Status != 0) // No ACK from chip + { + p_printf(("IIC Write: no ACK from Slave\r\n")); + return 1; + } + Status = iic_write(reg_addr); // Register address + if(Status != 0) // No ACK from chip + { + p_printf(("IIC Write: no ACK from Slave\r\n")); + return 1; + } + Status = iic_write(reg_val); // Register data + if(Status != 0) // No ACK from chip + { + p_printf(("IIC Write: no ACK from Slave\r\n")); + return 1; + } + iic_stop(); + return 0; +} + + +int iic_read8(unsigned char chip_addr, unsigned char reg_addr, unsigned char *data) +{ + int Status = 0; + + iic_start(); + Status = iic_write(chip_addr << 1); // Chip addr & Write + if(Status != 0) // No ACK from chip + { + p_printf(("IIC Write: no ACK from Slave\r\n")); + return 1; + } + Status = iic_write(reg_addr); // Register address + if(Status != 0) // No ACK from chip + { + p_printf(("IIC Write: no ACK from Slave\r\n")); + return 1; + } + iic_start(); // Repeated start + Status = iic_write((chip_addr << 1) | 0x01); // Chip addr & Read + if(Status != 0) // No ACK from chip + { + return 1; + } + *data = iic_read(1); // NACK + iic_stop(); + return 0; +} + +#endif + +/*----------------------------------------------------------------------------*/ +/* Platform independent functions */ +int iic_write8_mask(unsigned char chip_addr, unsigned char reg_addr, unsigned char reg_val, unsigned char mask) +{ + int Status; + u8 rd_val; + + if(mask == 0xFF){ // All bits + iic_write8(chip_addr, reg_addr, reg_val); + } + else{ // Write by mask + Status = iic_read8(chip_addr, reg_addr, &rd_val); + if(Status != XST_SUCCESS){ + return Status; + } + rd_val &= ~mask; // Clear bits to write + rd_val |= reg_val & mask; // Set bits by mask + Status = iic_write8(chip_addr, reg_addr, rd_val); + if(Status != XST_SUCCESS){ + return Status; + } + } + return XST_SUCCESS; +} + +int iic_write16(unsigned char chip_addr, unsigned short reg_addr, unsigned char reg_val) +{ + int Status; + u8 page, addr; + static int _last_page = -1; + + page = (u8) (reg_addr >> 8); + #ifdef DEBUG_MSG + p_printf(("iic_write16: addr 0x%04x data 0x%02x page 0x%02x (0x%02x) addr 0x%02x \r\n", reg_addr, reg_val, page, _last_page, (reg_addr & 0xFF))); + #endif + + if (_last_page < 0 || _last_page != page) { // New page + #ifdef DEBUG_MSG + p_printf(("p\r\n")); + #endif + Status = iic_write8(chip_addr, 0x01, page); + if (Status != XST_SUCCESS) { + p_printf(("iic_write16 page write failure\r\n")); + return XST_FAILURE; + } + } + _last_page = page; + + #ifdef DEBUG_MSG + p_printf(("r\r\n")); + #endif + addr = (u8) reg_addr & 0xFF; + Status = iic_write8(chip_addr, addr, reg_val); + if (Status != XST_SUCCESS) { + p_printf(("iic_write16 reg write failure\r\n")); + return XST_FAILURE; + } + return Status; +} + +int iic_read16(unsigned char chip_addr, unsigned short reg_addr, unsigned char *reg_val) +{ + int Status; + u8 page, addr; + static int _last_page = -1; + + page = (u8) (reg_addr >> 8); + #ifdef DEBUG_MSG + p_printf(("iic_read16: addr 0x%04x page 0x%02x (0x%02x) addr 0x%02x\r\n", reg_addr, page, _last_page, (reg_addr & 0xFF))); + #endif + + if (_last_page < 0 || _last_page != page) { // New page + #ifdef DEBUG_MSG + p_printf(("p\r\n")); + #endif + Status = iic_write8(chip_addr, 0x01, page); + if (Status != XST_SUCCESS) { + p_printf(("iic_read16 page write failure\r\n")); + return XST_FAILURE; + } + } + _last_page = page; + + #ifdef DEBUG_MSG + p_printf(("r\r\n")); + #endif + addr = (u8) reg_addr & 0xFF; + Status = iic_read8(chip_addr, addr, reg_val); + if (Status != XST_SUCCESS) { + p_printf(("iic_read16 reg read failure\r\n")); + return XST_FAILURE; + } + return Status; +} +/*----------------------------------------------------------------------------*/ diff --git a/lib/sw_apps/zynq_fsbl/src/te_iic_platform.h b/lib/sw_apps/zynq_fsbl/src/te_iic_platform.h new file mode 100644 index 0000000000..fd8f8ee13b --- /dev/null +++ b/lib/sw_apps/zynq_fsbl/src/te_iic_platform.h @@ -0,0 +1,62 @@ +/* +-- Company: Trenz Electronic +-- Engineer: Oleksandr Kiyenko / John Hartfiel + */ +#ifndef IIC_PLATFORM_H_ +#define IIC_PLATFORM_H_ +#include "xparameters.h" + +/* Include board specific settings */ +// #include "te_iic_define.h" +#include "te_iic_define_te0715.h" +// #include "te_iic_define_te0820.h" +// #include "te_iic_define_te0712.h" + +/* Enable extra Debug messages */ +//#define DEBUG_MSG +/*----------------------------------------------------------------------------*/ +int iic_init(void); +int iic_write8(unsigned char chip_addr, unsigned char reg_addr, unsigned char reg_val); +int iic_read8(unsigned char chip_addr, unsigned char reg_addr, unsigned char *reg_val); +int iic_write8_mask(unsigned char chip_addr, unsigned char reg_addr, unsigned char reg_val, unsigned char mask); +int iic_write16(unsigned char chip_addr, unsigned short reg_addr, unsigned char reg_val); +int iic_read16(unsigned char chip_addr, unsigned short reg_addr, unsigned char *reg_val); +void iic_delay(int delay_ms); +/*----------------------------------------------------------------------------*/ +#ifdef IIC_TYPE_AXI_IIC +#include "xiic.h" +#endif /* IIC_TYPE_AXI_IIC */ +/*----------------------------------------------------------------------------*/ +#ifdef IIC_TYPE_ZYNQPS_IIC +#include "xiicps.h" +#include +#include +XIicPs I2cInstancePtr; +#endif /* IIC_TYPE_ZYNQPS_IIC */ +/*----------------------------------------------------------------------------*/ +#ifdef IIC_TYPE_ZYNQUPS_IIC +#include "xiicps.h" +#include +#include +XIicPs I2cInstancePtr; +#endif /* IIC_TYPE_ZYNQUPS_IIC */ +/*----------------------------------------------------------------------------*/ +#ifdef IIC_TYPE_MCS_GPIO_IIC +#include "xiomodule_l.h" +#include "xstatus.h" +#include "xio.h" +#define GPIO_OUT_REG XPAR_IOMODULE_SINGLE_BASEADDR + XGO_OUT_OFFSET +#define GPIO_IN_REG XPAR_IOMODULE_SINGLE_BASEADDR + XGI_IN_OFFSET +#endif /* IIC_TYPE_MCS_GPIO_IIC */ +/*----------------------------------------------------------------------------*/ +#ifdef IIC_TYPE_AXI_GPIO_IIC +#include "xgpio.h" +XGpio Gpio; +#endif /* IIC_TYPE_AXI_GPIO_IIC */ +/*----------------------------------------------------------------------------*/ +#ifdef IIC_TYPE_PS_GPIO_IIC +#include "xgpiops.h" +XGpioPs Gpio; +#endif /* IIC_TYPE_PS_GPIO_IIC */ +/*----------------------------------------------------------------------------*/ +#endif /* IIC_PLATFORM_H_ */ diff --git a/lib/sw_apps/zynq_fsbl/src/te_si5338.c b/lib/sw_apps/zynq_fsbl/src/te_si5338.c new file mode 100644 index 0000000000..c41f6beb5f --- /dev/null +++ b/lib/sw_apps/zynq_fsbl/src/te_si5338.c @@ -0,0 +1,78 @@ +/* +-- Company: Trenz Electronic +-- Engineer: Oleksandr Kiyenko / John Hartfiel + */ + +#include "te_si5338.h" + +#ifdef CLOCK_SI5338 +#include "te_uart.h" +#include "te_Si5338-Registers.h" + +int si5338_init(unsigned char chip_addr) +{ + int i; + u8 reg_val; + Reg_Data rd; + int Status; + + // p_printf(("Si5338 Init Start.\r\n")); + // iic_init(); + p_printf(("Si5338 Init Registers Write.\r\n")); + + // I2C Programming Procedure + iic_write8( chip_addr, 246, 0x01); //Hard reset + // Disable Outputs + iic_write8_mask( chip_addr, 230, EOB_ALL, EOB_ALL); // EOB_ALL = 1 + // Pause LOL + iic_write8_mask( chip_addr, 241, DIS_LOL, DIS_LOL); // DIS_LOL = 1 + // Write new configuration to device accounting for the write-allowed mask + for(i=0; iBaseAddress); + XUartPs_SetBaudRate(&Uart_Ps, UART_BAUDRATE); + while(!XUartPs_Recv(&Uart_Ps, &u, 1)){ + } + return u; +} +#endif /* UART_TYPE_ZYNQPS_UART */ +/*----------------------------------------------------------------------------*/ +#ifdef UART_TYPE_NO_UART +u8 uart_read_char(void){ + return 0; +} +#endif /* UART_TYPE_NO_UART */ +/*----------------------------------------------------------------------------*/ diff --git a/lib/sw_apps/zynq_fsbl/src/te_uart.h b/lib/sw_apps/zynq_fsbl/src/te_uart.h new file mode 100644 index 0000000000..f6dc11edf1 --- /dev/null +++ b/lib/sw_apps/zynq_fsbl/src/te_uart.h @@ -0,0 +1,40 @@ +/* +-- Company: Trenz Electronic +-- Engineer: Oleksandr Kiyenko / John Hartfiel + */ +#ifndef SRC_TE_UART_H_ +#define SRC_TE_UART_H_ + +#include "te_iic_platform.h" + +u8 uart_read_char(void); + +/*----------------------------------------------------------------------------*/ +#ifdef UART_TYPE_AXI_UARTLITE +#include "xil_printf.h" +#include "xuartlite.h" +#define p_printf(x) xil_printf x +XUartLite UartLite; +#endif /* UART_TYPE_AXI_UARTLITE */ +/*----------------------------------------------------------------------------*/ +#ifdef UART_TYPE_AXI_UART16550 +#include "xil_printf.h" +#include "xuartns550.h" +#include "xuartns550_i.h" +#define p_printf(x) xil_printf x +XUartNs550 UartNs550; +#endif /* UART_TYPE_AXI_UART16550 */ +/*----------------------------------------------------------------------------*/ +#if defined(UART_TYPE_ZYNQPS_UART) || defined(UART_TYPE_ZYNQUPS_UART) +#include "xil_printf.h" +#include "xuartps.h" +#define p_printf(x) xil_printf x +XUartPs Uart_Ps; +#endif /* UART_TYPE_ZYNQPS_UART */ +/*----------------------------------------------------------------------------*/ +#ifdef UART_TYPE_NO_UART +#define p_printf(x) +#endif /* UART_TYPE_NO_UART */ +/*----------------------------------------------------------------------------*/ + +#endif /* SRC_TE_UART_H_ */