Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2188600
date_generatedTue May 5 17:32:55 2020 os_platformWIN64
product_versionVivado v2018.1 (64-bit) project_id423d4f11e08743db8e7ab43fd912b8ea
project_iteration1 random_idf09013a395b55d228d148b621ea1a506
registration_idf09013a395b55d228d148b621ea1a506 route_designTRUE
target_devicexc7z045 target_familyzynq
target_packagefbg676 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-4810MQ CPU @ 2.80GHz cpu_speed2794 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
gui_handlers
basedialog_ok=13 basedialog_yes=2 boardchooser_board_table=1 constraintschooserpanel_create_file=1
createconstraintsfilepanel_file_name=2 createsrcfiledialog_file_name=1 definemodulesdialog_define_modules_and_specify_io_ports=7 definemodulesdialog_entity_name=1
expruntreepanel_exp_run_tree_table=1 filesetpanel_file_set_panel_tree=16 flownavigatortreepanel_flow_navigator_tree=10 gettingstartedview_create_new_project=1
mainmenumgr_floorplanning=2 mainmenumgr_io_planning=2 mainmenumgr_reports=6 mainmenumgr_tools=4
mainmenumgr_window=4 msgtreepanel_message_view_tree=1 pacommandnames_add_sources=2 pacommandnames_auto_update_hier=4
pacommandnames_ports_window=2 pacommandnames_save_design=2 paviews_code=1 projectnamechooser_project_name=1
removesourcesdialog_also_delete=1 signaltreepanel_signal_tree_table=16 srcchooserpanel_create_file=1 srcmenu_ip_hierarchy=4
stalerundialog_no=2 taskbanner_close=2
java_command_handlers
addsources=2 editdelete=1 newproject=1 runbitgen=2
savedesign=2 showview=3 viewtaskrtlanalysis=2
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=1 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
ibuf=1 lut1=1 obuf=1
pre_unisim_transformation
ibuf=1 lut1=1 obuf=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") confidence_level_clock_activity=High confidence_level_design_state=High
confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low confidence_level_overall=Low
customer=TBD customer_class=TBD devstatic=0.203965 die=xc7z045fbg676-1
dsp_output_toggle=12.500000 dynamic=0.431819 effective_thetaja=1.9 enable_probability=0.990000
family=zynq ff_toggle=12.500000 flow_state=routed heatsink=medium (Medium Profile)
i/o=0.426161 input_toggle=12.500000 junction_temp=26.2 (C) logic=0.001008
mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000
mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 mgtvccaux_total_current=0.000000 mgtvccaux_voltage=1.800000
netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.635784 output_enable=1.000000
output_load=5.000000 output_toggle=12.500000 package=fbg676 pct_clock_constrained=1.000000
pct_inputs_defined=0 platform=nt64 process=typical ram_enable=50.000000
ram_write=50.000000 read_saif=False set/reset_probability=0.000000 signal_rate=False
signals=0.004650 simulation_file=None speedgrade=-1 static_prob=False
temp_grade=commercial thetajb=4.0 (C/W) thetasa=3.4 (C/W) toggle_rate=False
user_board_temp=25.0 (C) user_effective_thetaja=1.9 user_junc_temp=26.2 (C) user_thetajb=4.0 (C/W)
user_thetasa=3.4 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000
vccadc_voltage=1.800000 vccaux_dynamic_current=0.017520 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.039104 vccaux_total_current=0.056624
vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.001631 vccbram_total_current=0.001631
vccbram_voltage=1.000000 vccint_dynamic_current=0.009658 vccint_static_current=0.052842 vccint_total_current=0.062500
vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000
vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000
vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000
vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000
vcco18_voltage=1.800000 vcco25_dynamic_current=0.156250 vcco25_static_current=0.001000 vcco25_total_current=0.157250
vcco25_voltage=2.500000 vcco33_dynamic_current=0.000000 vcco33_static_current=0.000000 vcco33_total_current=0.000000
vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.000000 vcco_ddr_static_current=0.000000 vcco_ddr_total_current=0.000000
vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.000000 vcco_mio0_static_current=0.000000 vcco_mio0_total_current=0.000000
vcco_mio0_voltage=1.800000 vcco_mio1_dynamic_current=0.000000 vcco_mio1_static_current=0.000000 vcco_mio1_total_current=0.000000
vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.000000 vccpaux_static_current=0.010330 vccpaux_total_current=0.010330
vccpaux_voltage=1.800000 vccpint_dynamic_current=0.000000 vccpint_static_current=0.016610 vccpint_total_current=0.016610
vccpint_voltage=1.000000 vccpll_dynamic_current=0.000000 vccpll_static_current=0.003000 vccpll_total_current=0.003000
vccpll_voltage=1.800000 version=2018.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=0 bufgctrl_util_percentage=0.00
bufhce_available=168 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=32 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=16 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=32 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=8 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=8 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=900 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_i_dci=0
diff_hstl_i_dci_18=0 diff_hstl_ii=0 diff_hstl_ii_18=0 diff_hstl_ii_dci=0
diff_hstl_ii_dci_18=0 diff_hstl_ii_t_dci=0 diff_hstl_ii_t_dci_18=0 diff_hsul_12=0
diff_hsul_12_dci=0 diff_mobile_ddr=0 diff_sstl12=0 diff_sstl12_dci=0
diff_sstl12_t_dci=0 diff_sstl135=0 diff_sstl135_dci=0 diff_sstl135_r=0
diff_sstl135_t_dci=0 diff_sstl15=0 diff_sstl15_dci=0 diff_sstl15_r=0
diff_sstl15_t_dci=0 diff_sstl18_i=0 diff_sstl18_i_dci=0 diff_sstl18_ii=0
diff_sstl18_ii_dci=0 diff_sstl18_ii_t_dci=0 hslvdci_15=0 hslvdci_18=0
hstl_i=0 hstl_i_12=0 hstl_i_18=0 hstl_i_dci=0
hstl_i_dci_18=0 hstl_ii=0 hstl_ii_18=0 hstl_ii_dci=0
hstl_ii_dci_18=0 hstl_ii_t_dci=0 hstl_ii_t_dci_18=0 hsul_12=0
hsul_12_dci=0 lvcmos12=0 lvcmos15=0 lvcmos18=0
lvcmos25=1 lvcmos33=0 lvdci_15=0 lvdci_18=0
lvdci_dv2_15=0 lvdci_dv2_18=0 lvds=0 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl12=0 sstl12_dci=0
sstl12_t_dci=0 sstl135=0 sstl135_dci=0 sstl135_r=0
sstl135_t_dci=0 sstl15=0 sstl15_dci=0 sstl15_r=0
sstl15_t_dci=0 sstl18_i=0 sstl18_i_dci=0 sstl18_ii=0
sstl18_ii_dci=0 sstl18_ii_t_dci=0 tmds_33=0
memory
block_ram_tile_available=545 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=1090 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=545 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
ibuf_functional_category=IO ibuf_used=1 lut1_functional_category=LUT lut1_used=1
obuf_functional_category=IO obuf_used=1
slice_logic
f7_muxes_available=109300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=54650 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=218600 lut_as_logic_fixed=0 lut_as_logic_used=1 lut_as_logic_util_percentage=<0.01
lut_as_memory_available=70400 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=437200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=0 register_as_flip_flop_util_percentage=0.00
register_as_latch_available=437200 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=218600 slice_luts_fixed=0 slice_luts_used=1 slice_luts_util_percentage=<0.01
slice_registers_available=437200 slice_registers_fixed=0 slice_registers_used=0 slice_registers_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=218600 lut_as_logic_fixed=0
lut_as_logic_used=1 lut_as_logic_util_percentage=<0.01 lut_as_memory_available=70400 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_flip_flop_pairs_available=218600 lut_flip_flop_pairs_fixed=0 lut_flip_flop_pairs_used=0 lut_flip_flop_pairs_util_percentage=0.00
slice_available=54650 slice_fixed=0 slice_used=1 slice_util_percentage=<0.01
slicel_fixed=0 slicel_used=0 slicem_fixed=0 slicem_used=1
unique_control_sets_used=0 using_o5_and_o6_fixed=0 using_o5_and_o6_used=0 using_o5_output_only_fixed=0
using_o5_output_only_used=0 using_o6_output_only_fixed=0 using_o6_output_only_used=1
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=153 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=0 ctrls=0 dsp=0
effort=2 estimated_expansions=918 ff=0 global_clocks=0
high_fanout_nets=0 iob=2 lut=1 movable_instances=3
nets=4 pins=6 pll=0 router_runtime=1.000000
router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z045fbg676-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=ButtonLed_PLSide -verilog_define=default::[not_specified]
usage
elapsed=00:00:42s hls_ip=0 memory_gain=568.895MB memory_peak=878.215MB