led_example

2019.08.03.22:42:58 Datasheet
Overview
  clk_0  led_example

All Components
   simple_led_0 simple_led 1.0
Memory Map
master
 avalon_master
  simple_led_0
avs_s0  0x00000000

bytes_to_packets

altera_avalon_st_bytes_to_packets v18.1
clk_0 clk   bytes_to_packets
  clk
clk_reset  
  clk_reset
out_packets_stream   master
  in_stream


Parameters

CHANNEL_WIDTH 8
CHANNEL_WIDTH_DERIVED 8
ENCODING 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

clk_0

clock_source v18.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

master

altera_avalon_packets_to_master v18.1
bytes_to_packets out_packets_stream   master
  in_stream
clk_0 clk  
  clk
clk_reset  
  clk_reset
avalon_master   simple_led_0
  avs_s0
out_stream   packets_to_bytes
  in_packets_stream


Parameters

EXPORT_MASTER_SIGNALS 0
FAST_VER 0
FIFO_DEPTHS 2
FIFO_WIDTHU 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

packets_to_bytes

altera_avalon_st_packets_to_bytes v18.1
master out_stream   packets_to_bytes
  in_packets_stream
clk_0 clk  
  clk
clk_reset  
  clk_reset


Parameters

CHANNEL_WIDTH 8
CHANNEL_WIDTH_DERIVED 8
ENCODING 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

simple_led_0

simple_led v1.0
master avalon_master   simple_led_0
  avs_s0
clk_0 clk  
  clock
clk_reset  
  reset


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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