DE2-115 FPGA Board Configuration

Pin Assignments:

CLOCK

LED

KEY

RS232

PS2 for Keyboard and Mouse

Pin Assignment Table:

CLOCK
Name	Location	Direction	Standard
CLOCK_50	Y2	input	3.3-V LVTTL
CLOCK2_50	AG14	input	3.3-V LVTTL
CLOCK3_50	AG15	input	3.3-V LVTTL

LED
Name	Location	Direction	Standard
LEDR[0]	G19	output	2.5 V
LEDR[1]	F19	output	2.5 V
LEDR[2]	E19	output	2.5 V
LEDR[3]	F21	output	2.5 V
LEDR[4]	F18	output	2.5 V
LEDR[5]	E18	output	2.5 V
LEDR[6]	J19	output	2.5 V
LEDR[7]	H19	output	2.5 V
LEDR[8]	J17	output	2.5 V
LEDR[9]	G17	output	2.5 V
LEDR[10]	J15	output	2.5 V
LEDR[11]	H16	output	2.5 V
LEDR[12]	J16	output	2.5 V
LEDR[13]	H17	output	2.5 V
LEDR[14]	F15	output	2.5 V
LEDR[15]	G15	output	2.5 V
LEDR[16]	G16	output	2.5 V
LEDR[17]	H15	output	2.5 V
LEDG[0]	E21	output	2.5 V
LEDG[1]	E22	output	2.5 V
LEDG[2]	E25	output	2.5 V
LEDG[3]	E24	output	2.5 V
LEDG[4]	H21	output	2.5 V
LEDG[5]	G20	output	2.5 V
LEDG[6]	G22	output	2.5 V
LEDG[7]	G21	output	2.5 V
LEDG[8]	F17	output	2.5 V

KEY
Name	Location	Direction	Standard
KEY[0]	M23	input	3.3-V LVTTL
KEY[1]	M21	input	3.3-V LVTTL
KEY[2]	N21	input	3.3-V LVTTL
KEY[3]	R24	input	3.3-V LVTTL

RS232
Name	Location	Direction	Standard
UART_TXD	G9	output	3.3-V LVTTL
UART_RXD	G12	input	3.3-V LVTTL
UART_RTS	G14	output	3.3-V LVTTL
UART_CTS	J13	input	3.3-V LVTTL

PS2 for Keyboard and Mouse
Name	Location	Direction	Standard
PS2_CLK	G6	inout	3.3-V LVTTL
PS2_DAT	H5	inout	3.3-V LVTTL
PS2_CLK2	G5	inout	3.3-V LVTTL
PS2_DAT2	F5	inout	3.3-V LVTTL

SDCARD
Name	Location	Direction	Standard
SD_CMD	AD14	inout	3.3-V LVTTL
SD_CLK	AE13	output	3.3-V LVTTL
SD_WP_N	AF14	input	3.3-V LVTTL
SD_DAT[0]	AE14	inout	3.3-V LVTTL
SD_DAT[1]	AF13	inout	3.3-V LVTTL
SD_DAT[2]	AB14	inout	3.3-V LVTTL
SD_DAT[3]	AC14	inout	3.3-V LVTTL

VGA
Name	Location	Direction	Standard
VGA_HS	G13	output	3.3-V LVTTL
VGA_VS	C13	output	3.3-V LVTTL
VGA_SYNC_N	C10	output	3.3-V LVTTL
VGA_CLK	A12	output	3.3-V LVTTL
VGA_BLANK_N	F11	output	3.3-V LVTTL
VGA_R[0]	E12	output	3.3-V LVTTL
VGA_R[1]	E11	output	3.3-V LVTTL
VGA_R[2]	D10	output	3.3-V LVTTL
VGA_R[3]	F12	output	3.3-V LVTTL
VGA_R[4]	G10	output	3.3-V LVTTL
VGA_R[5]	J12	output	3.3-V LVTTL
VGA_R[6]	H8	output	3.3-V LVTTL
VGA_R[7]	H10	output	3.3-V LVTTL
VGA_G[0]	G8	output	3.3-V LVTTL
VGA_G[1]	G11	output	3.3-V LVTTL
VGA_G[2]	F8	output	3.3-V LVTTL
VGA_G[3]	H12	output	3.3-V LVTTL
VGA_G[4]	C8	output	3.3-V LVTTL
VGA_G[5]	B8	output	3.3-V LVTTL
VGA_G[6]	F10	output	3.3-V LVTTL
VGA_G[7]	C9	output	3.3-V LVTTL
VGA_B[0]	B10	output	3.3-V LVTTL
VGA_B[1]	A10	output	3.3-V LVTTL
VGA_B[2]	C11	output	3.3-V LVTTL
VGA_B[3]	B11	output	3.3-V LVTTL
VGA_B[4]	A11	output	3.3-V LVTTL
VGA_B[5]	C12	output	3.3-V LVTTL
VGA_B[6]	D11	output	3.3-V LVTTL
VGA_B[7]	D12	output	3.3-V LVTTL

Audio
Name	Location	Direction	Standard
AUD_ADCLRCK	C2	inout	3.3-V LVTTL
AUD_ADCDAT	D2	input	3.3-V LVTTL
AUD_DACLRCK	E3	inout	3.3-V LVTTL
AUD_DACDAT	D1	output	3.3-V LVTTL
AUD_XCK	E1	output	3.3-V LVTTL
AUD_BCLK	F2	inout	3.3-V LVTTL

I2C for Audio
Name	Location	Direction	Standard
I2C_SCLK	B7	output	3.3-V LVTTL
I2C_SDAT	A8	inout	3.3-V LVTTL

SDRAM
Name	Location	Direction	Standard
DRAM_BA[0]	U7	output	3.3-V LVTTL
DRAM_BA[1]	R4	output	3.3-V LVTTL
DRAM_DQM[0]	U2	output	3.3-V LVTTL
DRAM_DQM[1]	W4	output	3.3-V LVTTL
DRAM_DQM[2]	K8	output	3.3-V LVTTL
DRAM_DQM[3]	N8	output	3.3-V LVTTL
DRAM_RAS_N	U6	output	3.3-V LVTTL
DRAM_CAS_N	V7	output	3.3-V LVTTL
DRAM_CKE	AA6	output	3.3-V LVTTL
DRAM_CLK	AE5	output	3.3-V LVTTL
DRAM_WE_N	V6	output	3.3-V LVTTL
DRAM_CS_N	T4	output	3.3-V LVTTL
DRAM_DQ[0]	W3	inout	3.3-V LVTTL
DRAM_DQ[1]	W2	inout	3.3-V LVTTL
DRAM_DQ[2]	V4	inout	3.3-V LVTTL
DRAM_DQ[3]	W1	inout	3.3-V LVTTL
DRAM_DQ[4]	V3	inout	3.3-V LVTTL
DRAM_DQ[5]	V2	inout	3.3-V LVTTL
DRAM_DQ[6]	V1	inout	3.3-V LVTTL
DRAM_DQ[7]	U3	inout	3.3-V LVTTL
DRAM_DQ[8]	Y3	inout	3.3-V LVTTL
DRAM_DQ[9]	Y4	inout	3.3-V LVTTL
DRAM_DQ[10]	AB1	inout	3.3-V LVTTL
DRAM_DQ[11]	AA3	inout	3.3-V LVTTL
DRAM_DQ[12]	AB2	inout	3.3-V LVTTL
DRAM_DQ[13]	AC1	inout	3.3-V LVTTL
DRAM_DQ[14]	AB3	inout	3.3-V LVTTL
DRAM_DQ[15]	AC2	inout	3.3-V LVTTL
DRAM_DQ[16]	M8	inout	3.3-V LVTTL
DRAM_DQ[17]	L8	inout	3.3-V LVTTL
DRAM_DQ[18]	P2	inout	3.3-V LVTTL
DRAM_DQ[19]	N3	inout	3.3-V LVTTL
DRAM_DQ[20]	N4	inout	3.3-V LVTTL
DRAM_DQ[21]	M4	inout	3.3-V LVTTL
DRAM_DQ[22]	M7	inout	3.3-V LVTTL
DRAM_DQ[23]	L7	inout	3.3-V LVTTL
DRAM_DQ[24]	U5	inout	3.3-V LVTTL
DRAM_DQ[25]	R7	inout	3.3-V LVTTL
DRAM_DQ[26]	R1	inout	3.3-V LVTTL
DRAM_DQ[27]	R2	inout	3.3-V LVTTL
DRAM_DQ[28]	R3	inout	3.3-V LVTTL
DRAM_DQ[29]	T3	inout	3.3-V LVTTL
DRAM_DQ[30]	U4	inout	3.3-V LVTTL
DRAM_DQ[31]	U1	inout	3.3-V LVTTL
DRAM_ADDR[0]	R6	output	3.3-V LVTTL
DRAM_ADDR[1]	V8	output	3.3-V LVTTL
DRAM_ADDR[2]	U8	output	3.3-V LVTTL
DRAM_ADDR[3]	P1	output	3.3-V LVTTL
DRAM_ADDR[4]	V5	output	3.3-V LVTTL
DRAM_ADDR[5]	W8	output	3.3-V LVTTL
DRAM_ADDR[6]	W7	output	3.3-V LVTTL
DRAM_ADDR[7]	AA7	output	3.3-V LVTTL
DRAM_ADDR[8]	Y5	output	3.3-V LVTTL
DRAM_ADDR[9]	Y6	output	3.3-V LVTTL
DRAM_ADDR[10]	R5	output	3.3-V LVTTL
DRAM_ADDR[11]	AA5	output	3.3-V LVTTL
DRAM_ADDR[12]	Y7	output	3.3-V LVTTL