
State Machine - |top|niosMemM10:u0|niosMemM10_sdram_controller:sdram_controller|m_next
Name m_next.010000000 m_next.000010000 m_next.000001000 m_next.000000001 
m_next.000000001 0 0 0 0 
m_next.000001000 0 0 1 1 
m_next.000010000 0 1 0 1 
m_next.010000000 1 0 0 1 

State Machine - |top|niosMemM10:u0|niosMemM10_sdram_controller:sdram_controller|m_state
Name m_state.100000000 m_state.010000000 m_state.001000000 m_state.000100000 m_state.000010000 m_state.000001000 m_state.000000100 m_state.000000010 m_state.000000001 
m_state.000000001 0 0 0 0 0 0 0 0 0 
m_state.000000010 0 0 0 0 0 0 0 1 1 
m_state.000000100 0 0 0 0 0 0 1 0 1 
m_state.000001000 0 0 0 0 0 1 0 0 1 
m_state.000010000 0 0 0 0 1 0 0 0 1 
m_state.000100000 0 0 0 1 0 0 0 0 1 
m_state.001000000 0 0 1 0 0 0 0 0 1 
m_state.010000000 0 1 0 0 0 0 0 0 1 
m_state.100000000 1 0 0 0 0 0 0 0 1 

State Machine - |top|niosMemM10:u0|niosMemM10_sdram_controller:sdram_controller|i_next
Name i_next.111 i_next.101 i_next.010 i_next.000 
i_next.000 0 0 0 0 
i_next.010 0 0 1 1 
i_next.101 0 1 0 1 
i_next.111 1 0 0 1 

State Machine - |top|niosMemM10:u0|niosMemM10_sdram_controller:sdram_controller|i_state
Name i_state.111 i_state.101 i_state.011 i_state.010 i_state.001 i_state.000 
i_state.000 0 0 0 0 0 0 
i_state.001 0 0 0 0 1 1 
i_state.010 0 0 0 1 0 1 
i_state.011 0 0 1 0 0 1 
i_state.101 0 1 0 0 0 1 
i_state.111 1 0 0 0 0 1 

State Machine - |top|niosMemM10:u0|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_read_valid_state
Name avmm_read_valid_state.READ_VALID_IDLE avmm_read_valid_state.READ_VALID_PRE_READING avmm_read_valid_state.READ_VALID_READING 
avmm_read_valid_state.READ_VALID_IDLE 0 0 0 
avmm_read_valid_state.READ_VALID_READING 1 0 1 
avmm_read_valid_state.READ_VALID_PRE_READING 1 1 0 

State Machine - |top|niosMemM10:u0|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state
Name read_state.READ_STATE_PULSE_SE read_state.READ_STATE_CLEAR read_state.READ_STATE_FINAL read_state.READ_STATE_READY read_state.READ_STATE_DUMMY read_state.READ_STATE_SETUP read_state.READ_STATE_ADDR read_state.READ_STATE_IDLE 
read_state.READ_STATE_IDLE 0 0 0 0 0 0 0 0 
read_state.READ_STATE_ADDR 0 0 0 0 0 0 1 1 
read_state.READ_STATE_SETUP 0 0 0 0 0 1 0 1 
read_state.READ_STATE_DUMMY 0 0 0 0 1 0 0 1 
read_state.READ_STATE_READY 0 0 0 1 0 0 0 1 
read_state.READ_STATE_FINAL 0 0 1 0 0 0 0 1 
read_state.READ_STATE_CLEAR 0 1 0 0 0 0 0 1 
read_state.READ_STATE_PULSE_SE 1 0 0 0 0 0 0 1 

State Machine - |top|niosMemM10:u0|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state
Name erase_state.ERASE_STATE_ERROR erase_state.ERASE_STATE_RESET erase_state.ERASE_STATE_WAIT_DONE erase_state.ERASE_STATE_WAIT_BUSY erase_state.ERASE_STATE_ADDR erase_state.ERASE_STATE_IDLE 
erase_state.ERASE_STATE_IDLE 0 0 0 0 0 0 
erase_state.ERASE_STATE_ADDR 0 0 0 0 1 1 
erase_state.ERASE_STATE_WAIT_BUSY 0 0 0 1 0 1 
erase_state.ERASE_STATE_WAIT_DONE 0 0 1 0 0 1 
erase_state.ERASE_STATE_RESET 0 1 0 0 0 1 
erase_state.ERASE_STATE_ERROR 1 0 0 0 0 1 

State Machine - |top|niosMemM10:u0|altera_onchip_flash:onchip_flash|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state
Name write_state.WRITE_STATE_ERROR write_state.WRITE_STATE_RESET write_state.WRITE_STATE_WAIT_DONE write_state.WRITE_STATE_WAIT_BUSY write_state.WRITE_STATE_WRITE write_state.WRITE_STATE_ADDR write_state.WRITE_STATE_IDLE 
write_state.WRITE_STATE_IDLE 0 0 0 0 0 0 0 
write_state.WRITE_STATE_ADDR 0 0 0 0 0 1 1 
write_state.WRITE_STATE_WRITE 0 0 0 0 1 0 1 
write_state.WRITE_STATE_WAIT_BUSY 0 0 0 1 0 0 1 
write_state.WRITE_STATE_WAIT_DONE 0 0 1 0 0 0 1 
write_state.WRITE_STATE_RESET 0 1 0 0 0 0 1 
write_state.WRITE_STATE_ERROR 1 0 0 0 0 0 1 
