alt_sld_fab

2023.12.26.17:03:35 Datasheet
Overview

Memory Map

alt_sld_fab

alt_sld_fab v22.1


Parameters

DESIGN_HASH b8c92dc4476880b5b066
NODE_COUNT 1
MAX_WIDTH 25
SETTINGS {fabric sld dir agent mfr_code 70 type_code 34 version 3 instance 0 ir_width 2 psig 9b67919e}
CLOCKS {id {} }
AGENTS
EP_INFOS {hpath {niosMemM10:u0|niosMemM10_nios2:nios2|niosMemM10_nios2_cpu:cpu|niosMemM10_nios2_cpu_nios2_oci:the_niosMemM10_nios2_cpu_nios2_oci|niosMemM10_nios2_cpu_debug_slave_wrapper:the_niosMemM10_nios2_cpu_debug_slave_wrapper|sld_virtual_jtag_basic:niosMemM10_nios2_cpu_debug_slave_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst} }
MIRROR 0
TOP_HUB 1
COMPOSED_SETTINGS {fabric sld dir agent mfr_code 70 type_code 34 version 3 instance 0 ir_width 2 bridge_agent 0 prefer_host {} }
DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE Unknown
AUTO_DEVICE_SPEEDGRADE Unknown
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_presplit

altera_super_splitter v22.1


Parameters

MAX_WIDTH 25
SEND_WIDTHS 4
RECEIVE_WIDTHS 25
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_splitter

altera_sld_splitter v22.1
alt_sld_fab_presplit pass   alt_sld_fab_splitter
  nodes
alt_sld_fab_sldfabric clock_0  
  clock_0
node_0  
  node_0


Parameters

FRAGMENTS {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 2 23} {irq irq out 1 1} {ir_out ir_out out 2 2} } clock clock assign {debug.controlledBy {link_0} } moduleassign {debug.virtualInterface.link_0 {debug.endpointLink {fabric sld index 1} } } } }
EXAMPLE
ADD_INTERFACE_ASGN 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_jtagpins

altera_jtag_pins_bridge v22.1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_sldfabric

altera_sld_jtag_hub v22.1
alt_sld_fab_jtagpins clock   alt_sld_fab_sldfabric
  clock
node  
  node
clock_0   alt_sld_fab_splitter
  clock_0
node_0  
  node_0
ident   alt_sld_fab_ident
  ident_0


Parameters

DEVICE_FAMILY MAX10FPGA
SETTINGS {mfr_code 70 type_code 34 version 3 instance 0 ir_width 2 bridge_agent 0 prefer_host {} }
COUNT 1
N_SEL_BITS 1
N_NODE_IR_BITS 4
NODE_INFO 00011001000100000100011000000000
COMPILATION_MODE 0
BROADCAST_FEATURE 0
FORCE_IR_CAPTURE_FEATURE 1
FORCE_PRE_1_4_FEATURE 0
NEGEDGE_TDO_LATCH 1
ENABLE_SOFT_CORE_CONTROLLER 0
TOP_HUB 1
CONN_INDEX 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_ident

altera_connection_identification_hub v22.1
alt_sld_fab_sldfabric ident   alt_sld_fab_ident
  ident_0


Parameters

DESIGN_HASH b8c92dc4476880b5b066
COUNT 1
SETTINGS {width 4 latency 0}
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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