| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| u0|rst_controller_002|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller_002|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller_002 |
33 |
30 |
0 |
30 |
2 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller_001|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller_001 |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| u0|irq_mapper |
5 |
29 |
2 |
29 |
32 |
29 |
29 |
29 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_011|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_011 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_010|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_010 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 |
22 |
1 |
2 |
1 |
21 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_009 |
22 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 |
14 |
1 |
2 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_008 |
14 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_007 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_006 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_003|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_003|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_003|clock_xer |
126 |
0 |
0 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_003 |
128 |
2 |
0 |
2 |
122 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_002|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_002|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_002|clock_xer |
126 |
0 |
0 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_002 |
128 |
2 |
0 |
2 |
122 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_001|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_001|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_001|clock_xer |
126 |
0 |
0 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser_001 |
128 |
2 |
0 |
2 |
122 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser|clock_xer |
126 |
0 |
0 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|crosser |
128 |
2 |
0 |
2 |
122 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sdram_controller_s1_cmd_width_adapter |
127 |
3 |
0 |
3 |
104 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_cmd_width_adapter |
127 |
3 |
0 |
3 |
95 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sdram_controller_s1_rsp_width_adapter|uncompressor |
44 |
4 |
0 |
4 |
35 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sdram_controller_s1_rsp_width_adapter |
109 |
3 |
0 |
3 |
122 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_rsp_width_adapter|uncompressor |
44 |
4 |
0 |
4 |
35 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_rsp_width_adapter |
100 |
3 |
0 |
3 |
122 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001|arb|adder |
44 |
22 |
0 |
22 |
22 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001|arb |
15 |
0 |
4 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux_001 |
1334 |
0 |
0 |
0 |
132 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux|arb|adder |
48 |
24 |
0 |
24 |
24 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux|arb |
16 |
0 |
4 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_mux |
1455 |
0 |
0 |
0 |
133 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_011 |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_010 |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_009 |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_008 |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_007 |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_006 |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_005 |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_004 |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_003 |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_002 |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux_001 |
124 |
1 |
2 |
1 |
122 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|rsp_demux |
125 |
4 |
2 |
4 |
243 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_011|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_011|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_011 |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_010|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_010|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_010 |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_009|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_009|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_009 |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_008|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_008|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_008 |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_007|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_007|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_007 |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_006|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_006|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_006 |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_005|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_005|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_005 |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_004|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_004|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_004 |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_003|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_003|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_003 |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_002 |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux_001 |
124 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_mux |
245 |
0 |
0 |
0 |
123 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_demux_001 |
134 |
121 |
2 |
121 |
1332 |
121 |
121 |
121 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|cmd_demux |
135 |
144 |
2 |
144 |
1453 |
144 |
144 |
144 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sdram_controller_s1_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter |
106 |
6 |
8 |
6 |
104 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sdram_controller_s1_burst_adapter |
106 |
0 |
0 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter |
97 |
6 |
8 |
6 |
95 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_burst_adapter |
97 |
0 |
0 |
0 |
95 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_013|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_013 |
112 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_012|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_012 |
112 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_011|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_011 |
94 |
0 |
2 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_010|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_010 |
85 |
0 |
2 |
0 |
95 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_009|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_009 |
112 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_008|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_008 |
112 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_007|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_007 |
112 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_006|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_006 |
112 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_005|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_005 |
112 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_004|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_004 |
112 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_003|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_003 |
112 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_002|the_default_decode |
0 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_002 |
112 |
0 |
2 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_001|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router_001 |
112 |
0 |
6 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router|the_default_decode |
0 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|router |
112 |
0 |
6 |
0 |
122 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|spi_g_sensor_spi_control_port_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|spi_g_sensor_spi_control_port_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|spi_g_sensor_spi_control_port_agent |
309 |
39 |
49 |
39 |
325 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|spi_flash_spi_control_port_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|spi_flash_spi_control_port_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|spi_flash_spi_control_port_agent |
309 |
39 |
49 |
39 |
325 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sdram_controller_s1_agent_rdata_fifo |
63 |
41 |
0 |
41 |
20 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sdram_controller_s1_agent_rsp_fifo |
134 |
39 |
0 |
39 |
93 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sdram_controller_s1_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sdram_controller_s1_agent |
241 |
22 |
33 |
22 |
254 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_agent_rsp_fifo |
125 |
39 |
0 |
39 |
84 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_agent |
207 |
13 |
25 |
13 |
218 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|uart_s1_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|uart_s1_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|uart_s1_agent |
309 |
39 |
49 |
39 |
325 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|pio_mode_s1_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|pio_mode_s1_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|pio_mode_s1_agent |
309 |
39 |
49 |
39 |
325 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|pio_led_s1_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|pio_led_s1_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|pio_led_s1_agent |
309 |
39 |
49 |
39 |
325 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|altpll_pll_slave_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|altpll_pll_slave_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|altpll_pll_slave_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|altpll_pll_slave_agent |
309 |
39 |
49 |
39 |
325 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_debug_mem_slave_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_debug_mem_slave_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_debug_mem_slave_agent |
309 |
39 |
49 |
39 |
325 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_flash_data_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_flash_data_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_flash_data_agent |
309 |
39 |
49 |
39 |
328 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_flash_csr_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_flash_csr_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_flash_csr_agent |
309 |
39 |
49 |
39 |
325 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sysid_control_slave_agent_rsp_fifo |
152 |
39 |
0 |
39 |
111 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sysid_control_slave_agent|uncompressor |
44 |
1 |
0 |
1 |
42 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sysid_control_slave_agent |
309 |
39 |
49 |
39 |
325 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_instruction_master_agent |
192 |
42 |
90 |
42 |
144 |
42 |
42 |
42 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_data_master_agent |
192 |
42 |
90 |
42 |
144 |
42 |
42 |
42 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|spi_g_sensor_spi_control_port_translator |
92 |
22 |
41 |
22 |
56 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|spi_flash_spi_control_port_translator |
92 |
22 |
41 |
22 |
56 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sdram_controller_s1_translator |
73 |
4 |
3 |
4 |
61 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_memory_s1_translator |
55 |
7 |
10 |
7 |
36 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|uart_s1_translator |
92 |
22 |
41 |
22 |
57 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|pio_mode_s1_translator |
108 |
6 |
26 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|pio_led_s1_translator |
108 |
6 |
26 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|altpll_pll_slave_translator |
108 |
6 |
23 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_debug_mem_slave_translator |
108 |
5 |
16 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_flash_data_translator |
111 |
4 |
7 |
4 |
90 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|onchip_flash_csr_translator |
108 |
6 |
24 |
6 |
69 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|sysid_control_slave_translator |
108 |
6 |
24 |
6 |
35 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_instruction_master_translator |
109 |
51 |
0 |
51 |
101 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0|nios2_data_master_translator |
109 |
12 |
0 |
12 |
101 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u0|mm_interconnect_0 |
396 |
0 |
0 |
0 |
416 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|uart|the_niosMemM10_uart_regs |
41 |
8 |
6 |
8 |
39 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u0|uart|the_niosMemM10_uart_rx|the_niosMemM10_uart_rx_stimulus_source |
13 |
0 |
12 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|uart|the_niosMemM10_uart_rx |
15 |
1 |
0 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|uart|the_niosMemM10_uart_tx |
23 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|uart |
26 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|sysid |
3 |
17 |
2 |
17 |
32 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u0|spi_g_sensor |
25 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|spi_flash |
27 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|sdram_controller|the_niosMemM10_sdram_controller_input_efifo_module |
45 |
0 |
0 |
0 |
45 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|sdram_controller |
45 |
1 |
1 |
1 |
39 |
1 |
1 |
1 |
16 |
0 |
0 |
0 |
0 |
| u0|pio_mode |
7 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|pio_led |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory|the_altsyncram|auto_generated|mux2 |
34 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory|the_altsyncram|auto_generated|decode3 |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory|the_altsyncram|auto_generated |
26 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory |
30 |
1 |
1 |
1 |
8 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_flash|altera_onchip_flash_block |
34 |
2 |
0 |
2 |
36 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_flash|avmm_data_controller|sector_convertor |
3 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_flash|avmm_data_controller|sector_address_write_protection_checker |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_flash|avmm_data_controller|access_address_write_protection_checker |
28 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_flash|avmm_data_controller|address_convertor |
23 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_flash|avmm_data_controller|address_range_checker |
23 |
5 |
0 |
5 |
1 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_flash|avmm_data_controller |
126 |
6 |
2 |
6 |
76 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_flash|avmm_csr_controller |
47 |
4 |
4 |
4 |
64 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_flash |
93 |
0 |
0 |
0 |
66 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_debug_slave_wrapper|the_niosMemM10_nios2_cpu_debug_slave_sysclk |
43 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_debug_slave_wrapper|the_niosMemM10_nios2_cpu_debug_slave_tck |
131 |
0 |
1 |
0 |
45 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_debug_slave_wrapper |
123 |
0 |
0 |
0 |
50 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_ocimem|niosMemM10_nios2_cpu_ociram_sp_ram|the_altsyncram|auto_generated |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_ocimem|niosMemM10_nios2_cpu_ociram_sp_ram |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_ocimem |
92 |
0 |
6 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_avalon_reg |
48 |
0 |
28 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_im |
54 |
38 |
51 |
38 |
47 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_pib |
0 |
36 |
0 |
36 |
36 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_fifo|the_niosMemM10_nios2_cpu_nios2_oci_fifo_cnt_inc |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_fifo|the_niosMemM10_nios2_cpu_nios2_oci_fifo_wrptr_inc |
4 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_fifo|the_niosMemM10_nios2_cpu_nios2_oci_compute_input_tm_cnt |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_fifo |
115 |
0 |
65 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_dtrace|niosMemM10_nios2_cpu_nios2_oci_trc_ctrl_td_mode |
9 |
0 |
6 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_dtrace |
110 |
0 |
99 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_itrace |
24 |
52 |
22 |
52 |
53 |
52 |
52 |
52 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_dbrk |
95 |
0 |
0 |
0 |
99 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_xbrk |
61 |
5 |
58 |
5 |
6 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_break |
51 |
36 |
6 |
36 |
71 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci|the_niosMemM10_nios2_cpu_nios2_oci_debug |
50 |
1 |
30 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_nios2_oci |
170 |
0 |
0 |
0 |
69 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|niosMemM10_nios2_cpu_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|niosMemM10_nios2_cpu_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|niosMemM10_nios2_cpu_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|niosMemM10_nios2_cpu_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu|the_niosMemM10_nios2_cpu_test_bench |
309 |
3 |
275 |
3 |
33 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2|cpu |
149 |
1 |
29 |
1 |
125 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|nios2 |
149 |
0 |
0 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|altpll|sd1 |
3 |
1 |
0 |
1 |
6 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|altpll|stdsync2|dffpipe3 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|altpll|stdsync2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|altpll |
48 |
40 |
30 |
40 |
34 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
| u0 |
9 |
6 |
0 |
6 |
35 |
6 |
6 |
6 |
16 |
0 |
0 |
0 |
0 |