Attention: For security reasons,please choose a user name *different* from your login name.
Also make sure to choose a secure password and change it regularly.

Main Menu

Recent posts

Trenz Electronic FPGA Modules / Re: S7Mini program flash
Last post by JH - October 04, 2023, 07:34:27 AM
you must generate mcs file which includes your bitstream.
Trenz Electronic FPGA Modules / Re: TE0720 QSPI programming af...
Last post by JH - October 04, 2023, 07:32:22 AM
you must change boot.scr script and put it on the correct place in the QSPI(use amd default offset or change it on the config)
we have some notes and links to boot.scr usage:
CYC1000 community projects / Re: Spirit Level example desig...
Last post by allegedcape - September 28, 2023, 10:29:25 AM
Thanks a lot! this tips is very useful for me.
Trenz Electronic FPGA Modules / Re: TE0726 -ZynqBerry Power Pi...
Last post by Waldi3141 - September 28, 2023, 10:05:24 AM

power can also be supplied through PIN 2 and 4 of the J8 Header. Electrically the same.

best regards

Trenz Electronic FPGA Modules / TE0726 -ZynqBerry Power Pins
Last post by zaknahhas - September 27, 2023, 10:24:20 AM
Hallo all,
in the Wiki and the Manual of the TE0726. it is mentioned that the board could be powered from the J5 with 5v, which I am doing since years.
Is there negative side to power the board from PINS 2 and 4 on the J8 or there is some reason for not doing that ? Electrically they are connected together, but only J5 is mentioned in the provided info.

Thanks in advance
Trenz Electronic FPGA Modules / TEBF0808 / TE0807 SFP+ Etherne...
Last post by tom_kean - September 26, 2023, 04:33:16 PM

I'm trying to make the TE0807/TEBF0808 combination work with Xilinx AXI Ethernet subsystem cores driving the two SFP+ ports with 1000Base-X modules.  Is there an 'official' reference design or device tree for Petalinux which configures all the necessary motherboard resources to use the SFP+ ports (i.e. SI5345 clock chip, I2C expander which drives the SFP+ control/status signals and SFP+ sockets I2C)?

Thanks in advance.
Trenz Electronic FPGA Modules / Re: TE0720_TE0701_Petalinux_bo...
Last post by Neliz - September 26, 2023, 11:56:22 AM
Just to add on this, my TE0720-03-61C33MA does not contain the eMMC Nand flash memory U15. Not sure if this is an issue.
Trenz Electronic FPGA Modules / Re: Modifying TE0714 to use lo...
Last post by Vadim Y - September 26, 2023, 10:00:24 AM
Hello Martin,

It is indeed possible to change the VCCIO_0 voltage from 3.3V to 1.8V by replacing certain resistors. However, the main problem is that FLASH S25FL127SABMFV10 only works with a supply voltage of 3.3V. To convert, you will also have to change this component to 1.8V compatible.

Please remember that such interference with the operation of the module automatically voids your warranty.

Best regards,
Trenz Electronic FPGA Modules / TE0720_TE0701_Petalinux_boot
Last post by Neliz - September 25, 2023, 03:49:15 PM
Hi everyone,

I have a TE0720-03-61C33MA mounted on a TE0701-06.
When working on this board I have no problem with flashing bare metal applications with uart communication, but starting Petalinux shows its difficulties.

The problem I now face is that I receive no UART communication when trying to boot Petalinux. I am trying to do this via the SD card (note that programming via JTAG was not possible because the DDR pin was kept in reset mode).
When following:, I follow the "Launch" paragraph and copy image.ub, boot.src and Boot.bin from the delivery binary folder generated by the on a FAT32 partition SD card.
I have used the Vivado, Vitis, Petalinux 2022.2 version.
According the the documentation of the TE0701, when its finds an SD card it should automatically boot load from the SD card.
When I insert the SD card, the red LED on the TE0720 starts blinking slow, but no signal is received on the UART.
Is there an other way to see if the Zynq is booting from the SD card (maybe another LED or something)?
When opening the HW manager in Vivado it indicates that nothing is programmed.

The switches on the S3 are in default configuration (On is towards the middle of the PCB):
S3-1 OFF
S3-2 OFF
S3-3 ON
S3-4 OFF

Anyone has any idea if i'm doing something wrong/ forgetting something.
UltraScale / TE0803 PS GTR PLL lock
Last post by m1104 - September 22, 2023, 02:12:46 PM

I try to get PS GTR,  PCIe Endpoint working with a FreeRTOS based system. Currently I work in Vitis 2021.2 System Debugger.

I read somewhere that the PS GTR refclk should be stable before POR_B release, so
the idea is to configure the TE0803 Si5338 via I2C in main firmware (not FSBL), then restart the debugging session and hopefully see the GTR PLL lock with a value of 0x10.
But this is not the case. Should that approach be feasible ? At the moment I cannot see the GTR PLL lock. The psu_init.tcl is used as init sequence for the Debug session.

I think the Si5338 should keep the configuration after programming once and no power off, is that correct ?

In Vivado PCIe Ref Clk 2 is selected for the PS GTR, which routes to Si5338 output 3 on TE0803. All outputs currently configured with 100MHz, 1v8, LVDS, SSC., Input IN3/I2C_LSB with 25.0 MHz.

Is there any register to verify the clocking status ?