Recent posts

#11

Trenz Electronic FPGA Modules / Re: TE0802 as PCIe device

Last post by garliciris - July 04, 2024, 11:19:57 AM

To stop the generation of the SSD_RCLK signal from the CDCI6214 on the TE0802 module, you would typically need to reprogram the configuration of the CDCI6214 IC itself. The CDCI6214 is a clock generator/synchronizer IC that can be configured via its control inputs to output various clock signals. That's what advice I can give you

#12

Trenz Electronic FPGA Modules / Re: TE0820+HDMI701

Last post by JH - July 04, 2024, 06:43:58 AM

Hi,
which kind of monitor did you use?
Can you share boot log?
br
John

#13

Trenz Electronic FPGA Modules / Re: TE0820 Module Compatablity

Last post by Waldi3141 - July 02, 2024, 11:29:20 AM

Hello mer,

since the main chip is the same, it is likely that the design will work with the new board or rather that you can adopt most of your old stuff. Except for the things that have changed
The DDR chip (model and size) - You can compare your settings with the ones we have online on the current reference design 2023.2 - TE0820-05-3AE81MA is supported:
https://wiki.trenz-electronic.de/display/PD/TE0820+Test+Board

Also the qspi flash and emmc chip have changed, but they will probably work without many design changes.

More troublesome could be the new cpld firmware/different firmware versions(default/optional). How your application reacts to that depends on how the relevant signals are controlled on your carrier, especially the configuration signals.
https://wiki.trenz-electronic.de/display/PD/TE0820+CPLD+Firmware
https://wiki.trenz-electronic.de/display/PD/TE0820+TRM#TE0820TRM-ConfigurationSignals

#14

Trenz Electronic FPGA Modules / Re: TE0820+HDMI701

Last post by PaulChang - July 02, 2024, 08:27:23 AM

Hi John,

Thank you for your support.
Now it can login root via terminal. But the HDMI still no output.
Any

Best Regards,
Paul

#15

Trenz Electronic FPGA Modules / Re: FSBL hangs when initializi...

Last post by Stonebull - July 01, 2024, 03:19:16 PM

Okay great, thanks for the info.

Best Regards

#16

Trenz Electronic FPGA Modules / Re: TE0820+HDMI701

Last post by JH - July 01, 2024, 11:32:22 AM

Hi,
this demo designs need also file system on SD Card. You can use Win32 DiskImager and image from te0820-ubuntu.zip to prepare SD Card with correct partitions. After partitions are created bis DiskImager, copy Boot.bin and image.ub to the fat32 partition of the SD card. Image Download:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0820/Reference_Design/2019.2/HDMI701
--> te0820-ubuntu.zip
br
John

#17

Trenz Electronic FPGA Modules / TE0820 Module Compatablity

Last post by mer - June 28, 2024, 06:29:30 PM

I have a currently implemented project using TE0820-02-03CG-1EA module. Looking to move this project to TE0820-05-3AE81MA module.

The question is, will the vivado reference design for the 03CG board be valid and still work with the 3AE81MA module? At the very least might have to change RAM settings. But I'm mostly unsure about the CPLD configuration. Or am I destined to have to rebuild from the ground up from the new reference design? Thanks for any help.

#18

UltraScale / Re: Does Trenz have Master XDC...

Last post by JH - June 28, 2024, 09:25:47 AM

Hi,
best way is you start with our reference design:
https://wiki.trenz-electronic.de/display/PD/TE0745+Test+Board
It's for Vivado 23.2 and includes Board files for basic PS setting and some petalinux example and also prebuilt binaries to test your HW directly.
I would recommend to use 23.2 when you start, than it's easier to use our reference design with all sources.
For PL IO, you can use AMD IO planner, correct Pin Names are available in our schematics or pinout table. IO Standard for PL IOs depends on your connected periphery (the most pins goes only to simple Pin header).
Pinout table:
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Pinout
-->
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Pinout/TE0745_series_pinout_tracelength.xlsx

br
John

#19

UltraScale / Re: Does Trenz have Master XDC...

Last post by Reymon - June 27, 2024, 02:00:26 AM

Hello, I am a beginner FPGA programmer, I tried to do the same, using the XDC file (Vivado 2024.1) to configure the inputs/outputs like I do with Avnet (ZedBoard) or Digilent (Nexys 4) boards. I'm wondering if you successfully created your own XDC or 'part0_pins.xml' files for the TE0820 SOM and TE0701 carrier board. If yes, could you please tell me what procedure you followed?

I have a carrier board TEB0745-02 and TE0745-02-30-1IA SOM.

#20

Trenz Electronic FPGA Modules / Re: FSBL hangs when initializi...

Last post by JH - June 26, 2024, 12:43:48 PM

Hi,
yes simple remove this part of the code for PLL programming. You will not damage the board. This part is like a example in case you want to reprogramm PLL on power up. TE0715 PLL is preprogramm with following CLKS:
https://wiki.trenz-electronic.de/display/PD/TE0715+TRM#TE0715TRM-ProgrammableClockGenerator
it's the same output CLK frequence like on the example reprogramming on runtime.


br
John