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#11
UltraScale / TE0808/TE0803 Linux - Unable t...
Last post by logmaster - January 17, 2024, 03:30:52 PM
Hello Everyone,

I am currently facing a problem with Vivado 2019.2, Petalinux 2019.2 and TE0808/TE0803 on the TEBF0808 carrier board:

I was able to successfully export my custom design (.xsa) from Vivado and build the petalinux project I got from the StarterKit. The image that was created is booting properly. The issue occurs when I try to either execute an application which maps a physical address space to virtual memory using mmap, or when I try to run cat /proc/iomem


it both cases the kernel crashes and I get an error message saying:
Unable to handle paging request at virtual address ...
I can understand that maybe the custom app that I am using to access memory is faulty, but why running cat /proc/iomem is leading to the same issue?
Have some of you encountered something similar? I have not used any custom files, like the FSBL, from the StarterKit, only the custom petalinux project.

Any tips will be appreciated!
Thank you!
#12
Trenz Electronic FPGA Modules / Re: TE0820 as PS-PCIe Endpoint...
Last post by pema - January 16, 2024, 02:10:34 PM
Well, this doesn't look like a very approached subject.
Perhaps because EP in this SOC is not as much used as RC. Also perhaps because  PCI Express CEM Specification defines a 100-msec rule from the de-assertion time of the PERST# (slot reset) to the time that a PCI Express root complex (host) is allowed to probe the connected downstream endpoint.
At the time being Xilinx/AMD does not provide  the device driver for PCIe EP controller. Just for Host/RC.
This could perhaps be modified to EP as well and make it usable in the PCI EP Framework.

https://github.com/Xilinx/linux-xlnx/blob/master/drivers/pci/controller/pcie-xilinx-nwl.c


#13
Trenz Electronic FPGA Modules / Re: TE0820 as PS-PCIe Endpoint...
Last post by pema - January 10, 2024, 11:23:14 AM
Hi there again,
well I am now back to the ps-pcie EP issue. I remembered I disabled the NWL bridge controller drivers(since in this was being said to work only for the Root complex mode). 
The problem is if I disable the NWL PCIe Core drivers the device is no longer found on (therefor no probe takes place). If I enable them and I try to write to the BARs I get :

nwl-pcie fd0e0000.pcie: Unsupported request Detected


In Baremetal I was able to perform a basic example and get the PCIe EP to work based on the https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/pciepsu/examples/xpciepsu_ep_enable_example.c

I realize that this is perhaps a question that should be directed to AMD/Xilinx rather than Trenz, but perhaps you have already used the TR0820 +TEF1002 as EP with Linux. Or perhaps you already have a demo for the TEF1002 carrier board?
I would appreciate any help.
Best



#14
UltraScale / Re: TE0807 Starterkit referenc...
Last post by michielm - January 05, 2024, 12:56:05 PM
At last i found the culprit. It was the FSBL (ZYNQMP_FSBL.elf) not being properly configured (rebuild) for the hardware changes I made to the block design (PL).
You must be aware that as soon as you change the hardware (vivado block design) the FSBL needs to be rebuild. The default FSBL generated by the petalinux-build tool is not ok.
#15
UltraScale / Re: Reference Design & Custom ...
Last post by JH - January 03, 2024, 07:35:07 AM
Good to hear that it works now.
Regarding your question to PLL programming. NVM of SI5338 and also SI5345 are not preprogrammed.
br
John
#16
Trenz Electronic FPGA Modules / Re: use prebuilt files
Last post by JH - January 03, 2024, 07:33:24 AM
Hi,
it's correct, when you see only digilent serial number and no device than you has some problem between FTDI and AMD SoC oder SoC itself.
TE0790 DIPS are correct.
S1-3 DIP is set to ON and S1-4 is set to off (you wrote on it the first post, but it must be on (it's inverted))? And your SD Card is formatted as FAT32?
And which kind of external power supply did you use? what's the max. current limit?
br
John
#17
MAX1000 community projects / Re: SD Ram Controller for MAX1...
Last post by philippe69 - December 27, 2023, 09:24:43 AM
I found a solution.
1/ Install the altera_avalon_new_sdram_controller from the 20.1 Quartus
Copy the sdram controller in the quartus folder :
C:\intelFPGA_lite\22.1\ip\altera\sopc_builder_ip\altera_avalon_new_sdram_controller

In bonus, you can get the altera_avalon_new_sdram_controller from the 17.0 Quartus to obtain the sdram list used in the max1000.
Copy TEI0001_sdram_controller.qprs memory in the altera_avalon_new_sdram_controller.qprs file

In the file C:\intelFPGA_lite\22.1\ip\altera_components.ipx add the altera_avalon_new_sdram_controller
<component
   name="altera_avalon_new_sdram_controller"
   file="sopc_builder_ip/altera_avalon_new_sdram_controller/altera_avalon_new_sdram_controller_hw.tcl"
   displayName="SDRAM Controller"
   version="20.1"
   ...

After these operation you will see the SDRAM ip in the QSYS Memory and interface IP Catalog.

2/ Create your design in QSYS
The important thing to know is in the altpll use for the sdram clock MUST have -5000ps of clock phase shift (see the screen capture)
I saw that in the test_board design provides by Trenz :
https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/2.5x6.15/TEI0001/Reference_Design/20.1/test_board/TEI0001-test_board-quartus_20.1.1-20210709113644.zip

3/ Find enclose my simple design that is using :
- A Nios programe to light the 4 first leds. It uses user button
- a sdram use
- a verilog program to light the 4 last led

Philippe69
#18
UltraScale / Re: Reference Design & Custom ...
Last post by jwil - December 22, 2023, 10:36:52 PM
Following up, after booting the TEBF80818/TE0818, I was able to generate a configuration for the SI5338 and program over I2C to pass an output clock on J32.
#19
UltraScale / Re: Reference Design & Custom ...
Last post by jwil - December 22, 2023, 05:00:00 PM
Thank you for the pointers.

One follow-up question on clocks:

If I understand the TEBF0818 / TE0818 reference design correctly, the SI5345 OUT8 differential output is connected to SI5338 IN1/IN2.
Further, the SI5338 CLK1A output is connected to an external SMA connector (J32).

I am trying to program the SI5338 to pass input IN1/IN2 to output CLK1A to verify SI5338 operation.

Is there a default SI5338 configuration included in the reference design?
#20
Trenz Electronic FPGA Modules / Re: use prebuilt files
Last post by Lilly_567 - December 21, 2023, 04:36:56 PM
Hi,

Thanks a lot for your reply. Sadly, it is still not working. I now use the files from the correct folder (sorry for that stupid mistake). I left the JTAG Chain switched to the SoC. The DIP Switches on TE0790-03 are still S1 ON, S2 OFF, S3 OFF and S4 ON. I did not change them since I have the board. I tried using only the hello boot.bin as well as the one with the linux boot (boot.bin, image.ub and boot). However, both seem to not work. LED D2 is not switched of either, so I guess the Linux boot does not work. Putty does open a connection, but nothing arrives. I used Speed 115200 as required in your TRM.

I searched a little bit more online and found this: https://forum.digilent.com/topic/21535-arty-a7-board-vivado-20202-labtools-27-2269-no-devices-detected-on-target-localhost3121/

It looks very similar to my problem. The hardware target is found (with an address that looks ok), but not the device. In the end they found out they have a connectivity problem that is not easy to fix. In another forum (https://support.xilinx.com/s/question/0D52E00006iHlecSAC/vivado-kc705-jtag-no-devices-detected-on-target?language=en_US) they just said that the hardware is damaged. So I was sadly not able to find a solution with the hardware manager as well.

What else could I try? Is there a way to make sure my hardware is ok? I am really sorry that this is such trouble.

Kind regards,
Lilly