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TE0720 eFuse programming with TE0703 carrier board

Started by cfillot, July 30, 2018, 11:03:12 AM

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cfillot

Hello,

I would like to program Zynq eFuse with the xilskey library, but I have a problem with the JTAG chain.
I only read 0xFFFFFFFF IDCodes (as if the TDO signal was always high).

I use the following MIO ports, configured as GPIO:

  • MIO 10: TMS
  • MIO 11: TCK
  • MIO 12: TDI
  • MIO 13: TDO
  • MIO 7: MUX_SEL, with a value of 1 (to light up the green LED on TE0720)

I flashed the TE0703 CPLD with these modifications:

In the top.vhd file:

  C_TMS <= MIO10;
  C_TCK <= MIO11;
  C_TDI <= MIO12;
  MIO13 <= C_TDO;



In the LPF file I added:

IOBUF PORT "MIO10" BANK_VCCIO=3.3 IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "MIO11" BANK_VCCIO=3.3 IO_TYPE=LVCMOS33 PULLMODE=NONE ;
LOCATE COMP "MIO10" SITE "98" ;
LOCATE COMP "MIO11" SITE "97" ;


I made some tests using Xilinx GPIO primitives:
  - if in VHDL code I send output signals (MIO10, MIO11 or MIO12) to FL_0 LED, I can light up/down the LED.
  - if in VHDL code I assign '0' or '1' to MIO13, I can read it back.
=> The MIO routing between Zynq and TE0703 CPLD seems correct.

The problem seems to be with the C_xxx pins, which are routed to the TE0720 CPLD, but as I can access the FPGA and ARM with the Hardware Manager I think this part is working.

I also checked the Zynq CTRL register, DAP and JTAG chain are not disabled (https://www.xilinx.com/support/answers/64275.html).

Here is the C code using the libskey library:


static void check_efuse(void) {
XilSKey_EPl epl;
u32 status;

xil_printf("Trying to read eFUSE PL status...\r\n");
memset(&epl, 0, sizeof(epl));

/* Set MIO pins used to access JTAG */
epl.JtagMioMuxSel = 7;
epl.JtagMuxSelLineDefVal = 1;
epl.JtagMioTMS = 10;
epl.JtagMioTCK = 11;
epl.JtagMioTDI = 12;
epl.JtagMioTDO = 13;

/* Read eFUSE */
status = XilSKey_EfusePl_ReadKey(&epl);
if (status == XST_SUCCESS) {
xil_printf("Successfully read eFUSE PL!\r\n");
} else {
xil_printf("ERROR: status: 0x%08x (%u)\r\n", status, status);
}
}


Thanks in advance for any suggestion,

Christophe

cfillot

Well, I finally solved the problem by modifying the Xilskeyh library: I added a 50us delay in the setPin() function in xilskey_jscmd.c
I guess the two CPLD add a propagation delay whereas Xilinx guys made their tests with MIO pins directly connected to the JTAG port.

JH

Hi,

thanks for this notes with the delay in the xilinx lib.

br
John

lbahler

I have the same board and am trying to program the Efuse PL.  I need some assistance.  I am stuck.  The error I see is that JTag initialization is failing.  Is there some Trenz reference program that I could look at to see how to do this?

0x15

Quote from: cfillot on July 31, 2018, 01:58:19 PM
Well, I finally solved the problem by modifying the Xilskeyh library: I added a 50us delay in the setPin() function in xilskey_jscmd.c
I guess the two CPLD add a propagation delay whereas Xilinx guys made their tests with MIO pins directly connected to the JTAG port.

Would you mind to share your custom CPLD firmware?
Otherwise I need to download the 15GB for ISE ...
Thanks in advance!