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Board routing delay relative to CS, SCK and DQ0-3

Started by michealspencer, June 17, 2021, 04:54:37 AM

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michealspencer

Hi, I am using QSPI flash to store user data in unused for configuration and to limit Xilinx QSPI IP core, I need to know its latency parameter. Any help? Thanks!

JH

HI,
which module did you use?
QSPI is close to the FPGA on our modules, extra delay parameters are not needed normally.

br
John