Author Topic: TE0820 Power consumption reduction  (Read 317 times)

engkan2kit

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TE0820 Power consumption reduction
« on: June 04, 2021, 10:12:11 AM »
Hi,

I'm using the TE0820 4CG 2gb version. I currently using linux with 1 core. Most of the BSP from the reference design is intact. I'm getting around 750mA (3.3V VIN) of current. All available PL IOs are LVCMOS 1.8 where 1.8V VCCIO is supplied also by the 3.3V via a 1.8V regulator
Here's my setup:
1. using the si5334 to generate 100Mhz for the USB3.0
2. not using the SD card and eMMC. But eMMC is enabled.
3. not using Ethernet.
4. using the qSPI for storage (initramfs)
5. dropbear is running as well as rndis and the webdfu.
6. ram speed and cpu speed are the same from board_test design file.

Is there a way to further lower the consumption? Do you have a data on actual consumption of the clock circuit referenced by the USB3.0? Because I'm planning to replace this with a lower power 100Mhz XO in my custom board and just remove the inductors of the VCC of the XO and si5334 in the module.

Thank you.

JH

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Re: TE0820 Power consumption reduction
« Reply #1 on: June 08, 2021, 07:10:06 AM »
Hi,
zynqmp has a lot of mechanism to modify power consumption. Default a lot things are activated. Reduce fore example DDR bus size(use only half of DDR) and DDR speed and check PMU firmware. Disable also all interfaces which are not use (regenerate FSBL, and linux files).
Sorry I can't help much more on this topic.

Here is a little bit documentation, which maybe also helps:
https://www.xilinx.com/support/documentation/white_papers/wp482-zu-pwr-perf.pdf
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
--> see PMU part
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841813/Zynq%2BUltraScale%2BMPSoC%2BPower%2BManagement

br
John

engkan2kit

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Re: TE0820 Power consumption reduction
« Reply #2 on: September 26, 2021, 07:28:42 PM »
Hi JH,

Thanks for your the ideas. I'm trying to reduce to 16bits the effective bandwidth of the DD4 and nothing else is changed. I also checked the TE modified FSBL source code to check if I need to change anything related to DDR4 but there was none so I rebuilt my codes and I'm now not able to boot. The booting got stuck in FSBL. This is what it looks like:
--------------------------------------------------------------------------------
QSPI 32 bit Boot Mode
FlashID=0x20 0xBB 0x20
XFSBL_ERROR_QSPI_LENGTH
Device Copy Failed
Boot Device Initialization failed 0x19
Fsbl Error Status: 0x00002019
Performing FSBL FallBack

FSBL tried to copy files from QSPI but it looks like QSPI is not working now. So I'm guessing that the DDR4 is causing this not working anymore because only the DDR4 property was changed. Is there something I need to do on the PMU FW and FSBL to make this work on the T0820-4EV/4CG or do I need to remove components in the board?

Thank you.
« Last Edit: September 26, 2021, 08:19:11 PM by engkan2kit »

JH

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Re: TE0820 Power consumption reduction
« Reply #3 on: September 27, 2021, 06:36:37 AM »
Hi,
did you use clean Vitis project or did you simple update(sometime xsa update will not recognise all changes)? You should try to generate completely new Vitis workspace.
What did you change? Only bus width? Or more?
Did you run memory test over Vitis debug console? Does it work?

 I think something else was going wrong as you has changed DDR setting.

br
John



 

engkan2kit

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Re: TE0820 Power consumption reduction
« Reply #4 on: September 27, 2021, 08:14:53 AM »
Hi,

I'm just patching the fsbl from petalinux. So taking the TE mods apply it to the embeddedsw repo, generate a patch, then, add an fsbl recipe to apply the patch in petalinux project. This is working fine and I can get the si5338 related configs correctly. After setting bus width to half, I compared the changes in the Zynqmp IP and only 3 changes are there after changing the effective bus width to 16. The first 1 is the offsets, the 2nd is the property of bus-width, and the 3rd one is the psu_protection__slaves property where the the range of low DDR range was changed as well.

I'll try to setup a Vitis Workspace to do a memory test over the debug console. I had a Vitis workspace before but the flow takes to long just to generate the FSBL so I had to move it to petalinux.

Thanks.

JH

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Re: TE0820 Power consumption reduction
« Reply #5 on: September 27, 2021, 08:44:13 AM »
Hi,
Quote
I'm just patching the fsbl from petalinux.
I would not recommend this. I've heard from other customer, that FSBL from petalinux works different to FSBL from Vitis, when you add our changes as patch. Source code is the same, but maybe petalinux use other drivers or different compiler order or....


Quote
I'll try to setup a Vitis Workspace to do a memory test over the debug console. I had a Vitis workspace before but the flow takes to long just to generate the FSBL so I had to move it to petalinux.
I've some basic notes here:
https://wiki.trenz-electronic.de/display/PD/Vitis
It still not finish and Xilinx gas changed again style a little bit since I've start this documentation for Vitis, but it should help to find basic steps.

br
John

engkan2kit

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Re: TE0820 Power consumption reduction
« Reply #6 on: September 27, 2021, 05:32:07 PM »
Thanks John.

I used to use Vitis in generating the FSBL but build, compiling it is so slow and it's difficult to automate and change if we want to support different hardware.

I tried to build FSBL from Vitis just now and they have the same problem with the one I built with petalinux. It seems that I may have some other issues. I'll try to run the DRAM and MEM test applications. However I have not done this before with TE0820. Since I can't set TE0820 to JTAG mode (only SD and QSPI), do I need to flash memory test application to QSPI first?

Thanks.

JH

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Re: TE0820 Power consumption reduction
« Reply #7 on: Today at 08:09:04 AM »
Hi,
which Vivado/Vitis version did you use?
I've test it one time on my place and it works.
I've use our 2020.2 design:
https://wiki.trenz-electronic.de/display/PD/TE0820+Test+Board
1. create the project with the selection guide and 2020.2
2. open Block Design and select the ZynqMP IP --> go to memory and change effective dram bus width to 16
3. Generate bitstream -> use console and type TE::hw_build_design -export_prebuilt
4. Start Vitis generation with our scripts: TE::sw_run_vitis -all
use the new generated Hello TE0820 boot.bin from your assembly variant and boot from SD(is faster, QSPI should also work)

br
John