Hi,
I have a TE0720 module that I've integrated into a board. For some reason, when I turn the power on, the module rapidly cycles power on and off. If I probe the PGOOD pin, I can see it going low for about 50ms before going back high. Schematic and screenshot of PGOOD signal attached. I left the MODE and EN pins floating so they should go to default pull-up state. LED1 (red) flashes quickly. LED2 (green) blinks briefly each power cycle. Any ideas what this could be?
Thanks!!
Jacob
Hi,
i will check and let you now, if i can detect something.
PS: You should add pullups for EN and Mode Pin. There are internal pullups on cpld, but tey are weak.
br
John
Hi,
did you let pins unconnected and removed them from schematic symbol? Can you add Pin numbers? Have you paid attention that the connectors are are hermaphroditic?
- https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+LSHM+B2B+Connectors
I need the Pin numbers to all your connector pins.
For example:
TE0720 Module Pin <-> Your Carrier Pin
JM1-1 (VIN) <-> JB1-2 (3.3VIN)
JM1-3 (VIN) <-> JB1-4 (3.3VIN)
JM1-5 (VIN) <-> JB1-6 (3.3VIN)
ON your schematic, you has only one VIN Pin without Pinnumber on connector JB1.
For some overview, see also:
- https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide
JTAG Sel Pin is also not connected...
PS: You can also send a email with files to: support@trenz-electronic.de
br
John
Thanks John,
Yes, sorry about the schematic. Attached is one that shows pins. However, I did some more testing and am now thinking that the problem is the power supply. Also attached is a screenshot of the 3.3Vin (yellow) and PGOOD (green) signals. To me it looks like when the module tries to turn on it pulls the rail voltage too low. This is strange to me since this is the second iteration of a prototype board, and the first board had no problems with the Zynq (this also makes me think that it isn't a pinout issue). I will double check the pin mapping again to verify. Basically all components relating to the Zynq are the same. I did change the layout slightly, but (I thought) to make it more optimal... Let me know if you have any ideas.
- also, can you explain about the JTAG SEL pin? I don't know much about the JTAG protocol but I assumed all the JTAG pins should just be directly connected to the header as shown in the schematic (I use a Digilent HS3 for flashing).
Thanks,
Jacob
Hi,
better. I will check.
JTAG Sel: TE0720 has a CPLD. With this Pin you can switch between CPDL and FPGA access. If you set to GND only FPGA is available.
- https://wiki.trenz-electronic.de/display/PD/TE0720+TRM#TE0720TRM-SystemControllerCPLDI/OPins (https://wiki.trenz-electronic.de/display/PD/TE0720+TRM#TE0720TRM-SystemControllerCPLDI/OPins)
More detailed CPLD description is in planning.
br
John
Hi,
3.3VIN should be not lower that 3.135V
- https://wiki.trenz-electronic.de/display/PD/TE0720+TRM#TE0720TRM-RecommendedOperatingConditions (https://wiki.trenz-electronic.de/display/PD/TE0720+TRM#TE0720TRM-RecommendedOperatingConditions)
Is the NOSEQ floating? You should add Pullup or Pulldown, see also:
- https://wiki.trenz-electronic.de/display/PD/TE0720+TRM#TE0720TRM-PowerandPower-OnSequence
Can you check 3.3VIN with your REV01 PCB version.
Basis IO connections seems to be ok
br
John
Thanks for your help John. Indeed it was a power supply issue and nothing to do with the Zynq :) A battery management circuit was turning my power off.
Thanks again.
Jacob