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[set the value of the parameter XILTIMER_tick_timer to one of the Zynq HW timers]

#11

Trenz Electronic FPGA Modules / Re: Does TE0720 Ethernet work ...

Last post by viktornikolov - November 02, 2025, 01:19:15 PM

I still have no luck with a standalone app using the RAW lwIP API in Vitis 2025.1.

I made the standalone lwIP TCP Perf Client (RAW API) work in Vitis 2025.1. 🙂 The problem was in the timer configuration.

When you try to create the lwIP TCP Perf Client example in Vitis 2025.1, it tells you that you must set the BSP parameter XILTIMER_en_interval_timer to True. But that is wrong. This parameter can remain False. Instead, you must set the value of the parameter XILTIMER_tick_timer to one of the Zynq HW timers. (I will report this as a bug to AMD.)

With the tick_timer configured, the lwIP TCP Perf Client ran without issues. I achieved an average throughput of 831 Mbits/sec.
I added the project export to my GitHub.

The issue is that the main loop of the lwIP RAW API application relies on various counters to be updated every 50 ms. That is done in a function called by a timer interrupt.
The Vitis 2025.1 version of the code uses functions XTimer_SetInterval() and XTimer_SetHandler(). The initialization of the timer driver is done automatically and relies on the setting of the XILTIMER_tick_timer BSP parameter. Unfortunately, there is no proper error checking in the XTimer_* functions. They don't tell you that you are trying to call them on an uninitialized driver.

In Vitis 2024.2, the iperf client example uses the "old school" xscutimer.h API with explicit initialization and error checking. There is no dependency on BSP parameter settings.

[booting]

#12

UltraScale / Re: TE0821 with TE0706 Carrier...

Last post by harrx - October 31, 2025, 03:15:46 PM

Dear,

Could you please help me resolve some the on-boarding issues with TE0821  module(2CG1E- 4 GB DDR) with TE0706 board.

I started with the Test board design v2024.2. I am stuck at the stage of the booting.

My config:
Power: 5V, 1A
Dip switches S1: (1:'1', 2:'0', 3:'0' 4:'1') Default
Reference design:

1. Booting with SD Card: I followed the reference design procedure and copied the 3 required files to the SD card Boot (1st) Partition. Nothing in the Root (2nd) partition. As soon as I power up the device with SD card inserted, all LEDs (incl. Ethernet) starts blinking and I see only ? on the Serial terminal. Taking out the SD card, all LEDs are stable again.

2. QSPI Boot: TE::pr_program_flash -swapp u-boot ,, also does not work for me. I get the error "Flash programming is not supported in the selected boot mode". I tried switching S1-3:'1', but this does not help also.

3. Simple JTAG programming also does not work. Programming Baremetal application with Vitis also generates the error: "Flash programming is not supported in the selected boot mode, switch mode to JTAG".

Could you please help me resolve this issue. Point#03 is the most cirtical to be able to quickly load App changes from Vitis without the need to boot the whole device.

Best regards,
Haris.

[booting]

#13

UltraScale / Re: TE0821 with TE0706 Carrier...

Last post by harrx - October 31, 2025, 03:14:30 PM

Dear,

Could you please help me resolve some the on-boarding issues with TE0821  module(2CG1E- 4 GB DDR) with TE0706 board.

I started with the Test board design v2024.2. I am stuck at the stage of the booting.

My config:
Power: 5V, 1A
Dip switches S1: (1:'1', 2:'0', 3:'0' 4:'1') Default
Reference design:

1. Booting with SD Card: I followed the reference design procedure and copied the 3 required files to the SD card Boot (1st) Partition. Nothing in the Root (2nd) partition. As soon as I power up the device with SD card inserted, all LEDs (incl. Ethernet) starts blinking and I see only "-?-" on the Serial terminal. Taking out the SD card, all LEDs are stable again.

2. QSPI Boot: TE::pr_program_flash -swapp u-boot ,, also does not work for me. I get the error "Flash programming is not supported in the selected boot mode". I tried switching S1-3:'1', but this does not help also.

3. Simple JTAG programming also does not work. Programming Baremetal application with Vitis also generates the error: "Flash programming is not supported in the selected boot mode, switch mode to JTAG".

Could you please help me resolve this issue. Point#03 is the most cirtical to be able to quickly load App changes from Vitis without the need to boot the whole device.

Best regards,
Haris.

[booting]

#14

UltraScale / TE0821 with TE0706 Carrier Boa...

Last post by harrx - October 31, 2025, 03:13:18 PM

Dear,

Could you please help me resolve some the on-boarding issues with TE0821  module(2CG1E- 4 GB DDR) with TE0706 board.

I started with the Test board design v2024.2. I am stuck at the stage of the booting.

My config:
Power: 5V, 1A
Dip switches S1: (1:'1', 2:'0', 3:'0' 4:'1') Default
Reference design:

1. Booting with SD Card: I followed the reference design procedure and copied the 3 required files to the SD card Boot (1st) Partition. Nothing in the Root (2nd) partition. As soon as I power up the device with SD card inserted, all LEDs (incl. Ethernet) starts blinking and I see only "?" on the Serial terminal. Taking out the SD card, all LEDs are stable again.

2. QSPI Boot: TE::pr_program_flash -swapp u-boot ,, also does not work for me. I get the error "Flash programming is not supported in the selected boot mode". I tried switching S1-3:'1', but this does not help also.

3. Simple JTAG programming also does not work. Programming Baremetal application with Vitis also generates the error: "Flash programming is not supported in the selected boot mode, switch mode to JTAG".

Could you please help me resolve this issue. Point#03 is the most cirtical to be able to quickly load App changes from Vitis without the need to boot the whole device.

Best regards,
Haris.

#15

Arrow USB Programmer2 / Re: Step-by-step videos solvin...

Last post by Subcritical - October 31, 2025, 01:33:46 PM

[Español]

    En Linux, la mayor parte del tiempo está habilitado el propio controlador ftdi del nucleo del sistema operativo.
    Por lo tanto,al principio, necesitas deshabilitar (incorporar a la lista negra) el módulo del kernel ftdi_sio de Linux.Esto también ocurre si el fptdi tiene un controlador proporcionado para las placas Xilinx, precisamente diseñado para los entornos de diseño FPGA ISE o Vivado.

Este es el mismo módulo del kernel que estoy usando con bastante éxito y extensivamente en mis otros proyectos FPGA.

    Incorporar un controlador a la lista negra de este módulo del kernel impacta negativamente en otros trabajos que lo usen, es decir hay que siempre indicar que driver ftdi se usa, en el caso de max1000 o cyc1000 es el ft2232h con una configuración para la plataforma altera alvergada en la pequeña rom del ft2232h.

    Biblioteca utilizada para trabajar con el formato de vectores svf:
https://github.com/ORSoC/libxsvf

Para instalar esta biblioteca, necesitas compilar el código fuente.

Code Select Expand

make all
[English]
    In linux most of the time is enabled the own ftdi driver.
So at first, you need to disable (blacklist) the linux ftdi_sio kernel
module.

    This happens also if the fptdi has a driver provided to xilinx boards, that is for the ise or vivado fpga design suits.

    This is the very same kernel module that I am using quite successfully and
extensively with my other FPGA projects. Blacklisting this kernel module will likely
impact my other work in a negative fashion.

    Library used to play with vector format svf:
https://github.com/ORSoC/libxsvf

    To install this library you need compile the source.

Code Select Expand

    make all

[Deutsh]
    Unter Linux ist meistens der eigene FTDI-Treiber aktiviert.
Daher müssen Sie zunächst das Linux-Kernelmodul ftdi_sio deaktivieren (auf die schwarze Liste setzen).Dies passiert auch, wenn das FPTDI einen Treiber für Xilinx-Boards bereitstellt, der für die ISE- oder Vivado-FPGA-Design-Suiten gedacht ist.

    Dies ist dasselbe Kernelmodul, das ich sehr erfolgreich und umfangreich bei meinen anderen FPGA-Projekten einsetze. Das Blacklisten dieses Kernelmoduls wird wahrscheinlich meine andere Arbeit negativ beeinflussen.Bibliothek, die für das Arbeiten mit dem Vektorformat SVF verwendet wird:

https://github.com/ORSoC/libxsvfUm

   diese Bibliothek zu installieren, müssen Sie den Quellcode kompilieren.

Code Select Expand

make all


#16

Trenz Electronic FPGA Modules / Re: SDCARD Images download for...

Last post by eddydw - October 30, 2025, 09:29:32 PM

Thanks for the answers John.

That answers all my questions.

Best regards
Eddy

[TL;DR:]

#17

Trenz Electronic FPGA Modules / Re: Does TE0720 Ethernet work ...

Last post by viktornikolov - October 28, 2025, 07:23:01 PM

Networking works in Vitis 2025.1 in a FreeRTOS app!

TL;DR: Vitis 2025.1 forced me to enable the lwip220_lwip_dhcp_does_acd_check option, but it doesn't work with my MikroTik switches (not even in Vitis Classic 2024.2). After I disabled this option, the FreeRTOS lwIP TCP Perf Client worked perfectly. I achieved an average transfer speed of 566 Mbits/sec.
I made the project export publicly available here.

When you use any of the lwIP examples in Vitis 2025.1, it throws an error unless you set certain lwIP parameters to the values specified in the error message.



The thing is that the default values of lwIP parameters are chosen to save memory but are not optimal for performance. Vitis 2025.1 requires you to increase several parameter values to achieve high TCP Perf Client performance.

For some reason, AMD also decided to insist on enabling the parameter lwip220_lwip_dhcp_does_acd_check, which has nothing to do with performance.
In theory, with this parameter enabled, the lwIP stack should send an ARP probe to verify that the IP address it received via DHCP is not in use by another device on the network. I don't know how it's actually implemented in the code.
However, on my MikroTik switches (I tried two different ones), it doesn't work, and the lwIP prints a misleading error message "ERROR: DHCP request timed out".
(I tried an old TP-Link router, and the dhcp_does_acd_check works OK with it.)
I don't know what's wrong with my MirkoTik switch. I can use arping normally, so an ARP probe is not prohibited.

So, I must enable the lwip220_lwip_dhcp_does_acd_check so that Vitis 2025.1 will generate an lwIP example, and then I must disable it so that the example works with my MikroTik switch. 🙂

I still have no luck with a standalone app using the RAW lwIP API in Vitis 2025.1. It simply freezes after the Ethernet speed auto negotiation, even after I disabled the dhcp_does_acd_check option.

#18

MAX1000 community projects / Re: Playing ZX Spectrum in HDM...

Last post by Subcritical - October 28, 2025, 01:54:32 PM

original dominic-meads

dvi sinals I - señales dvi I- DVI-Signale I

dvi sinals II - señales dvi II- DVI-Signale II
[Español]
Vamos a adaptar el hdmi de la placa ATLAS o un conector generico hdmi de 8 pines para crear la cara sonriente de "VGA image driver (make a face) on an Intel FPGA"
El código original esta en la siguiente dirección:
https://github.com/dominic-meads/Quartus-Projects/tree/main/VGA_face

Es un ejercicio muy sencillo pero muy util para ver como dibujar en cada cuador de la imagen o "frame" rectángulos.
Para ello se definen coordenadas y desigualdades.

Sólo hay que cambiar la correspondencia de los pines asociados al HDMI y el reloj principal los hacemos paso a paso desde quartus y su pin planner.
El error se ha producido porque primero hay que cambiar de chip al chip usado en la supercpld max1000.

Los pines que hay que cambiar en las restricciones son:

## HDMI Direct ATLAS_V002_MAX1000                                 
set_location_assignment PIN_H5  -to # CLK-               
set_location_assignment PIN_K10 -to # CLK+ # canal del reloj dvi/hdmi
set_location_assignment PIN_H13 -to # 0-  # Negativo difierencial canal azul             
set_location_assignment PIN_J13 -to # 0+  # Positivo canal azul 
set_location_assignment PIN_K11 -to # 1-                 
set_location_assignment PIN_K12 -to # 1+  # canla verde
set_location_assignment PIN_J12 -to # 2-                 
set_location_assignment PIN_L12 -to # 2+  # canal rojo

##clocks ATLAS_V002_MAX1000
set_location_assignment PIN_H6 -to CLK_12MHZ

El envoltorio HDMI es el más simple que he usado y hay que poner a cero las señales negativas.
Es un DVI en realidad y muy sencillo.
Poniendo los pines a 0:
assign TMDS_D0_N=1'b0;
assign TMDS_D1_N=1'b0;
assign TMDS_D2_N=1'b0;
assign TMDS_CLK_N=1'b0;   


Cometimos el error de identificar incorrectamente el chip de la max1000, he puesto la misma familia pero de 2kles, ahora corrigo el error.

La serie max 10 es más moderna que la serie cyclone 10 Lp, sin cambiar las IPS propietarias de intel/altera vamos a ver si sintetiza el diseño para max1000.
Este ejercicio es realmente interesante para saber posicionar elementos en pantalla a través de HDMI/DVI.

[English]
We are going to adapt the HDMI from the ATLAS board or a generic 8-pin HDMI connector to create the smiling face of the "VGA image driver (make a face) on an Intel FPGA." 
The original code is located at the following address: 
https://github.com/dominic-meads/Quartus-Projects/tree/main/VGA_face 

It is a very simple exercise but very useful for seeing how to draw rectangles in each square of the image or "frame." 
Coordinates and inequalities are defined for this purpose. 

You only need to change the mapping of the pins associated with HDMI, and we will set up the main clock step by step from Quartus and its Pin Planner. 
The error occurred because you first need to switch from the chip to the chip used in the SuperCPLD MAX1000. 

The pins that need to be changed in the constraints are:
## HDMI Direct ATLAS_V002_MAX1000                                 
set_location_assignment PIN_H5  -to # CLK-               
set_location_assignment PIN_K10 -to # CLK+ # clock channel
set_location_assignment PIN_H13 -to # 0-                 
set_location_assignment PIN_J13 -to # 0+  # blue channel 
set_location_assignment PIN_K11 -to # 1-                 
set_location_assignment PIN_K12 -to # 1+  # green channel
set_location_assignment PIN_J12 -to # 2-                 
set_location_assignment PIN_L12 -to # 2+  # red channel

##clocks ATLAS_V002_MAX1000set_location_assignment PIN_H6 -to CLK_12MHZ

The HDMI wrapper is the simplest I have used, and the negative signals need to be set to zero.
It is actually a DVI and very simple.Setting the pins to 0:

assign TMDS_D0_N=1'b0;
assign TMDS_D1_N=1'b0;
assign TMDS_D2_N=1'b0;
assign TMDS_CLK_N=1'b0;   

We made the mistake of incorrectly identifying the chip of the max1000; I put the same family but with 2kles, now I am correcting the error.
The max 10 series is more modern than the cyclone 10 LP series. Without changing Intel/Altera's proprietary IPs, let's see if the design synthesizes for max1000.
This exercise is really interesting to know how to position elements on the screen via HDMI/DVI.

[Deutsch]
Wir werden den HDMI-Anschluss der ATLAS-Platine oder einen generischen 8-Pin-HDMI-Stecker anpassen, um das lächelnde Gesicht von ,,VGA-Bildtreiber (ein Gesicht machen) auf einem Intel FPGA" zu erstellen.
Der Originalcode befindet sich unter folgender Adresse:
https://github.com/dominic-meads/Quartus-Projects/tree/main/VGA_face.
Es ist eine sehr einfache, aber sehr nützliche Übung, um zu sehen, wie man Rechtecke in jedem Feld des Bildes oder ,,Frames" zeichnet. Dazu werden Koordinaten und Ungleichungen definiert.
Es müssen nur die Zuordnungen der mit HDMI verbundenen Pins geändert werden, und die Hauptuhr wird Schritt für Schritt über Quartus und seinen Pin Planner eingerichtet.
Der Fehler trat auf, weil man zuerst vom Chip zum verwendeten Chip auf der SuperCPLD MAX1000 wechseln muss. Die Pins, die in den Einschränkungen geändert werden müssen, sind:

## HDMI Direct ATLAS_V002_MAX1000                                 
set_location_assignment PIN_H5  -to # CLK-               
set_location_assignment PIN_K10 -to # CLK+ # positiver Kanal der Taktdifferenz des DVI-Signals
set_location_assignment PIN_H13 -to # 0-                 
set_location_assignment PIN_J13 -to # 0+  # blauer Differenzialkanal 
set_location_assignment PIN_K11 -to # 1-                 
set_location_assignment PIN_K12 -to # 1+  # positiver grün differenzieller Kanal
set_location_assignment PIN_J12 -to # 2-                 
set_location_assignment PIN_L12 -to # 2+  # roter Differenzialkanal 


##clocks ATLAS_V002_MAX1000set_location_assignment PIN_H6 -to CLK_12MHZ

Die HDMI-Hülle ist die einfachste, die ich je benutzt habe, und die negativen Signale müssen auf Null gesetzt werden. Es ist eigentlich ein DVI und sehr einfach. Die Pins auf 0 setzen:

assign TMDS_D0_N=1'b0;
assign TMDS_D1_N=1'b0;
assign TMDS_D2_N=1'b0;
assign TMDS_CLK_N=1'b0;

Wir haben den Fehler gemacht, den Chip des Max1000 falsch zu identifizieren.
Ich habe dieselbe Familie, aber von 2kles, verwendet, jetzt korrigiere ich den Fehler.
Die Max 10-Serie ist moderner als die Cyclone 10 LP-Serie. Ohne die proprietären IPs von Intel/Altera zu ändern, werden wir sehen, ob das Design für Max1000 synthetisiert werden kann.
Diese Übung ist wirklich interessant, um zu lernen, wie man Elemente auf dem Bildschirm über HDMI/DVI positioniert.

CaraSONRIENTE - Limpia - max1000.zip

#19

Trenz Electronic FPGA Modules / Re: TE0720-04-62I33MA QSPI pro...

Last post by JH - October 28, 2025, 08:35:51 AM

Hi,
load Uboot with over JTAG with xsct console,this should be:

Code Select Expand

connect
targets -set -filter {name =~ "Cortex-A9 #0"}
rst
dow fsbl.elf
con
# Wait until DDR init done, then stop CPU and load U-Boot:
stop
dow u-boot.elf
con
On Uboot load your boot.bin with tftp and write to the qspi flah. this should be somthing like this:

Code Select Expand

setenv serverip 192.168.1.1
setenv ipaddr 192.168.1.10
tftpboot 0x1000000 BOOT.BIN && \
sf probe 0 0 0 && \
sf erase 0x0 +${filesize} && \
sf write 0x1000000 0x0 ${filesize}

br
John

#20

Trenz Electronic FPGA Modules / Re: TE0745-03-81C31-A board sc...

Last post by JH - October 28, 2025, 08:26:56 AM

Dear Zhou,
schematics of the modules are available on the download area of our modules.
https://www.trenz-electronic.de/Downloads/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV03/Documents

We offer also altium project of our carrier, which you can use as startpoint for your own design:
https://www.trenz-electronic.de/Downloads/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/5.2x7.6_Carriers/TEB0745/REV02/HW_Design

br
John