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#11
Trenz Electronic FPGA Modules / Re: Detecting wrong speed grad...
Last post by neels - October 28, 2024, 12:00:27 PM
Hi John,

Thanks for your reply.

With regards to FSBL code, I have been looking at the 2021.2 reference design (https://shop.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0720/Reference_Design/2021.2/test_board/TE0720-test_board_noprebuilt-vivado_2021.2-build_11_20220202131838.zip) and specifically reading FSBL code from the below file to read the speed_grade, temperature_grade and model numbers.
TE0720-test_board_noprebuilt-vivado_2021.2-build_11_20220202131838.zip\test_board\sw_lib\sw_apps\zynq_fsbl\src\ te_fsbl_hooks_te0720.c

A few questions:

1. Is TE0720-test_board_noprebuilt-vivado_2021.2-build_11_20220202131838.zip\test_board\sw_lib\sw_apps\zynq_fsbl\src\ te_fsbl_hooks_te0720.c, the new version of FSBL you were referring to, or is there a new FSBL code somewhere else?

2. I have been looking in https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-SCregisters. But I couldn't find any reference to speed_grade temperature_grade and model numbers. Where can I find the values.

3. Can the older revision of boards have the CPLD firmware upgraded?


Thanks,
Neels   
#12
Trenz Electronic FPGA Modules / Re: Detecting wrong speed grad...
Last post by JH - October 28, 2024, 11:08:09 AM
Hi,
this SOM Information was only available for CPLD Revision smaller as 07. With CPLD revision 07 it was replaced with other information.
Newer CPLD code check Revision and shows different output. So I think you use a older version of the FSBL code or?

br
John
#13
Open source hardware / TE0726-04 ZynqBerry + zhdmi HD...
Last post by zerkman - October 26, 2024, 09:25:19 PM
Hello,

I've been lent a newly purchased TE0726, rev. 04 ZynqBerry board. I am trying to run my open source zhdmi HDMI transmitter core on it.

The problem is that I haven't been able to have the zhdmi demo running properly. It seems the output is incorrect HDMI, with the blue component getting the same levels as the red component. The audio is not playing correctly: the expected 440 Hz sine wave can be heard, but with many crackles.

My HDMI capture device does not recognise the signal, so I had to take a picture of the screen:
test-zynqberry.jpg

The correct image should be:
test-z7lite.png
(as captured from another board).

The demo project to obtain this display can be created as follows:
git clone https://github.com/zerkman/zhdmi
cd zhdmi/demo/vivado
VIVADO=/opt/Xilinx/Vivado/2024.1/bin/vivado ./create_project.sh zhdmi_demo_zynqberry
Of course, use the real path to your installed copy of Vivado.
I used Vivado 2024.1, but it should also work with other versions.

I believe I used the proper pin assignment constraints, as borrowed from one of the TE0726 demos.

Am I doing something wrong? Could someone try and tell me if they can reproduce the issue?
#14
Trenz Electronic FPGA Modules / Re: Detecting wrong speed grad...
Last post by neels - October 25, 2024, 01:36:12 PM
I repeated the above test with a couple of new TE0720-04-61C530A SOMs.
Below is what I see at the start of the FSBL when running with 2021.2 tools

--------------------------------------------------------------------------------
Xilinx First Stage Boot Loader (TE modified)
Release 2021.2  Oct  7 2024-09:10:51

Device IDCODE: 23727093
Device Name: 7z020 (7)
Device Revision: 2
--------------------------------------------------------------------------------
TE0720 TE_FsblHookBeforeHandoff_Custom

SoM: TE0720-03-0A14S SC REV:07
MAC: 80 34 28 86 77 D1

The results from the second module are below.

--------------------------------------------------------------------------------
Xilinx First Stage Boot Loader (TE modified)
Release 2021.2  Oct  7 2024-09:10:51

Device IDCODE: 23727093
Device Name: 7z020 (7)
Device Revision: 2
--------------------------------------------------------------------------------
TE0720 TE_FsblHookBeforeHandoff_Custom

SoM: TE0720-03-0A14S SC REV:07
MAC: 80 34 28 86 70 E1

I notice that for both the modules with newer revision numbers, The revision number, speed_grade and model numbers extracted by the FSBL are not matching the specification of the SOM modules.

Will be great if someone from Trenz can replicate this and clarify if something has changed when programming the board information for new revision of the TE0720 SOMs.
#15
Trenz Electronic FPGA Modules / Detecting wrong speed grade fr...
Last post by neels - October 23, 2024, 01:43:32 PM
I have been looking at detecting the speed grade of the Zynq Chip from the TE0720-04-61Q33MA SOMs.

From https://shop.trenz-electronic.de/en/TE0720-04-61Q33MA-SoC-Module-with-AMD-Zynq-7020-1Q-Automotive-1-GByte-DDR3-4-x-5-cm, it is clear that the
SOM has a Zynq chip with a speed grade -1.

The FSBL detects the device as following during startup. The speed grade appears to be wrong.
SoM: TE0720-03-0A LF SC REV:07
So, I did some investigation. From the trenz reference design (C:\Downloads\TE0720-test_board-vivado_2021.2-build_11_20220202131818\test_board\sw_lib\sw_apps\zynq_fsbl\src\te_fsbl_hooks_te0720.c line 245), speed_grade is evaluated as follows
 
speed_grade = (rval16 >> 14) & 3;
The rval16 value is read using phytool

./phytool read eth0/0x1A/4
0x3207

given rval16=0x3207, let's break down the operation:
First, we convert 0x3207 to binary:
0x3207 = 0011 0010 0000 0111
The operation is:
speed_grade = (rval16 >> 14) & 3;
Right-shifting by 14 positions:
0011 0010 0000 0111 >> 14 = 00
Performing bitwise AND with 3 (which is 11 in binary):
00 & 11 = 00
Converting the result back to decimal:
00 in binary = 0 in decimal
Therefore, given rval16=0x3207, the value of speed_grade is 0.

But as seen before, the device has a speedgrade of -1.

Am I missing something here ?

P.S: Just to double check, I did the same test on another module TE0720-04-61C530A ( https://shop.trenz-electronic.de/en/TE0720-04-61C530A-SoC-Module-with-AMD-Zynq-7020-1C-256-MByte-DDR3-SDRAM-4-x-5-cm
 I got the correct speedgrade
SoM: TE0720-03-1C  R SC REV:05
 Reading the registers through phytool
./phytool read eth0/0x1A/4
 0x4105
#16
Trenz Electronic FPGA Modules / Occasional boot from SD (Custo...
Last post by SES - October 23, 2024, 11:01:31 AM
Dear community,

We are currently working on a custom carrier board for a MPSoC Module with Xilinx Zynq UltraScale+ ZU7EV-1E (TRENZ board: TE0817-01-7DE21-A). We are booting Petalinux from the SD card, but the FPGA sometimes does not start up. As a result, not only PS_INIT_B is pulled low, but also there is no message shown in the UART terminal.

We have checked the following aspects so far:

- Schematics and layout of the custom carrier board
- Configuration of the mode pins (set to SD)
- Power-up sequence
- Configuration of the SD in PS side (Vivado project):
- Hardware configuration and device tree (Petalinux project):

In addition, we have followed the guide (https://adaptivesupport.amd.com/s/article/Need-help-with-boot-debug-on-Zynq-Ultrascale-or-Versal?language=en_US) for debugging the FPGA boot. As a result, we observed: FPGA boot debug

We would appreciate if someone could help us understand the reason behind this issue and a possible way to fix it.

Thanks in advance,
#17
Trenz Electronic FPGA Modules / Any idea?
Last post by Utred1978 - October 21, 2024, 09:43:02 AM
Hello, dear everybody,

I am new to FPGA and trying to communicate two TE0725 boards through optical fiber adapter. Actually in Vivado there are GTP transceiver IP core and also SGMII IP core which are only available for 7 series FPGAs with I/O banks 216. But those IPcores are not available for TE0725. I have also tried to write the IP cores by myself, but it is too difficult.

So I would like to ask which kind of tools or IPcores are available for communication between two TE0725 through the optical fiber adapter, and can also be connected to AXI bus.

Thank you very much.
#18
Trenz Electronic FPGA Modules / Re: TE0722 not detected by viv...
Last post by vertapple - October 18, 2024, 12:14:04 PM
Hey sorry I forgot to come back here. I managed to get it working. I believe it was solder damage (? not sure) but I swapped from the P1 and P2 connectors to the 3.3V and GND on J1. A friend noticed the power supply had read 3.25V the one time then 3.09V later on, hence we believe the soldering on P1 and P2 was bad/damaged the board.
 
#20
Trenz Electronic FPGA Modules / Using Gowin FPGA Designer for ...
Last post by watsicagaylord - October 18, 2024, 11:36:53 AM
Hello to all of you.

I'm attempting to create a testbench and run simulations with Gowin FPGA Designer, but I can't seem to locate the simulation option in the tools menu. Is there someone that can help me with the Gowin FPGA Designer simulation process? Regards!