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Trenz Electronic FPGA Modules / Re: TE0715 QSPI boot not worki...
Last post by JH - May 28, 2024, 01:38:25 PM
Mode Pin controls Boot mode and when you has it floating, I would expect QSPI boot Mode, because CPLD of TE0715 has week pullup activated. This should be OK normally, but it's not good to keep this floating.

Can you tell me how you connect all these controller pins on your carrier?

Can you tell me the LEDs when your appr. the module(firmware and some LED status signal has changed last year):

PS: Did you write also to the technical support?
UltraScale / Re: TEF1002-02 with TE0820-05
Last post by harrx - May 28, 2024, 01:27:55 PM
Hi Martin,

Yes thanks this worked. I had the same jumper positions, but somwhow switching them off and on again after connecting the JTAG makes the connection.
Trenz Electronic FPGA Modules / TE0715 QSPI boot not working
Last post by zhjaafri - May 28, 2024, 04:28:13 AM
I am using TE0715 module with our own designed carrier as per connections of TE0706. We have developed a program which works fine on both TE0706 and our developed pcb when programmed using jtag. But when we try to boot using qspi flash it works fine on TE0706 Board but does not works on our pcb. Although we have applied same settings for jtagen and mode pins for som. jtagen pin is set to gnd where as mode pin is left open and en1 pin is pulled up using 10k resistor.
suggest me solution for this problem.
UltraScale / Re: TEF1002-02 with TE0820-05
Last post by Martin R. - May 27, 2024, 10:32:15 AM

there are three dips (S2-4, S2-5, S2-6) associated with JTAG, they should all be in off position for JTAG access to SoC of TE0820.

There is one further dip which enables the module (S2-7) this should be in ON position. See
If this is not on also D4 on carrier should blink

Do you see 'unknown device' in vivado if switching to carrier cpld JTAG or module cpld JTAG?

The green LEDS on TEF1002 are D3 and D4? They should be constant on.

What do you mean by xilinx programmer method? You connected  programmer with fly-wires to J5?
J19 PJTAG is different and has to be enabled in the design.

did you try to just boot our pre-build reference design from SD card? Do you see anything on UART output?
UltraScale / Re: TE0820 -05-2AI21MA and TE0...
Last post by JH - May 24, 2024, 11:15:46 AM
you can ignore both messages. I don't know why the tool think it's a newer one available, but local one is the correct one for this reference design
 We update this board files only with newer vivado version and sometimes they are not backward compatible.
 In case of local repository, which will be set via trenz scripts for this project, you can also install/copy it into your vivado version(see point 3 or 4):

Regarding board interface. We didn't add board interfaces for the module, we add only basic PS configuration(see board automation, which will be done automatically on the reference design), which is also used on the reference design. PL design depends mostly on the carrier and customer design and so it makes not really sense to define pl interfaces.

UltraScale / TE0820 -05-2AI21MA and TE0701-...
Last post by for_those_about_to_code - May 17, 2024, 04:30:58 PM

First question on this board.

I have the above pieces of Hardware and I am working through the "Test Board" tutorial (2022.2 version).

I have ran (Ubuntu 20.04), selected '0' and then '107' for the corresponding component.

I notices that I get the following couple of lines:

WARNING: [Board 49-151] The current board '' is from a local repo. The vivado install has a corresponding board with version greater than or equal to the local repo board. Please use boards from vivado install to avoid any upgrade/migrate issues


INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI

A couple of questions...

1) How do I use the Installed version rather than the local repo version? 
2) Why do I get the "No Compatible Board Interface..." message?  As far as I can see I am selecting the correct device?

Thanks in advanced.
Trenz Electronic FPGA Modules / Re: TE0710 red SysLed flashing...
Last post by sjoshi - May 17, 2024, 01:39:30 PM
Me again. I have found the issue. Turns out that the design was done assuming that the XMOD will be connected upside down, meaning the odd and even pins were swapped. The second issue while using the TE0790 was the DIP switch 4. This is documented in the TE0706 documentation which was used as a reference design so it was easy to figure out.

Thanks for confirming that the Lattice FPGA has no role other than that what we had assumed.
Trenz Electronic FPGA Modules / Re: TE0710 red SysLed flashing...
Last post by sjoshi - May 17, 2024, 12:50:59 PM

I have tried connecting to the board by swapping TDI and TDO but I still get an error message saying that "No devices detected on target".

We are connecting a TE0790 to the carrier board. Are there any other configuration pins I might be missing?
Trenz Electronic FPGA Modules / Re: TE0710 red SysLed flashing...
Last post by JH - May 17, 2024, 10:35:55 AM
JTAGSEL bin you can switch between Lattice CPLD and AMD FPGA. JTAG SEL=0 is FPGA(JTAG will forwarded through the CPLD to the FPGA). In case you use JTAGSEL=1, you should see unknown device normaly on vivado HW Manager.

Which programmer did you use on your carrier board?

Check also TDI/TDO, maybe they are swapped in your design?

BOOTMODE or NOSEQ are optional for TE0710 with native FPGA on both available firmwares and are no matter for JTAG:
or older version for modules which was delivered before feb 2024:

Trenz Electronic FPGA Modules / Re: TE0710 red SysLed flashing...
Last post by sjoshi - May 16, 2024, 03:50:36 PM
I can program the module from a TE0705 board. When I plug the module in our carrier board and pull SC_nRST and EN1 high, the module configures itself from memory and my blinker code works. We seem to be missing JTAG access from our carrier board although I have read on the forum that the JTAG signals are simply patched through. JTAGSEL = 0 also seems to be the suggested setting.