- Welcome to Trenz Electronic GmbH Support Forum.
Recent posts
#21
Trenz Electronic FPGA Modules / Help Needed: Best Starter Setu...
Last post by davidmillerdavid - May 29, 2025, 07:23:52 AMHi everyone,
I am fairly new to working with Trenz boards and recently got the TE0715-04-30-2C module. I am planning to use it with Vivado 2023.1 on a Windows 11 setup. I have been through the Trenz Wiki but wanted to ask directly here :-
What is the recommended starting point in terms of reference designs or precompiled projects for this board: ??
Do I need to customize the board files for Vivado 2023.1 or are the default ones on GitHub still good to go: ??
Any advice on working with the PMOD interfaces or clock config on this module: ??
Would really appreciate input from anyone who has hands-on experience with this board. Just want to make sure I am starting off with the right setup and avoid rookie mistakes.
Thanks in advance!!
With Regards,
David
azure course in bangalore
I am fairly new to working with Trenz boards and recently got the TE0715-04-30-2C module. I am planning to use it with Vivado 2023.1 on a Windows 11 setup. I have been through the Trenz Wiki but wanted to ask directly here :-
What is the recommended starting point in terms of reference designs or precompiled projects for this board: ??
Do I need to customize the board files for Vivado 2023.1 or are the default ones on GitHub still good to go: ??
Any advice on working with the PMOD interfaces or clock config on this module: ??
Would really appreciate input from anyone who has hands-on experience with this board. Just want to make sure I am starting off with the right setup and avoid rookie mistakes.
Thanks in advance!!
With Regards,
David
azure course in bangalore
#22
UltraScale / Support Request for TE0808-05-...
Last post by cristina - May 28, 2025, 05:49:11 PMHi everyone 
,
I'm facing an issue with the TE0808-05-BBE81-E board (Zynq UltraScale+ XCZU15EG-1FFVC900E, 4GB DDR4) and I would appreciate any help or guidance.
System configuration:
Board: TE0808-05-BBE81-E
Processor: Xilinx Zynq UltraScale+ XCZU15EG-1FFVC900E
Memory: 4 GB DDR4 SDRAM
Development environment: Vivado 2022.1
Workflow followed:
1-I downloaded the Starter Kit project for the TE0808 from the official Trenz Electronics website and imported it into Vivado.
2-Connected to the hardware using:
3-open_hw_manager
4-connect_hw_server -url localhost:3121 -allow_non_jtag
5-Detected the device with get_hw_devices xczu15_0
6-Generated the bitstream (zusys_wrapper.bit) and .ltx file (zusys_wrapper.ltx) through the implementation (impl_1)
7-Programmed the device using program_hw_devices
Main issue:
Although the bitstream is successfully loaded (DONE status = 1), Vivado does not detect the VIO visualization cores—specifically the vio_general core. As a result, I am unable to visualize any signals in the Hardware Manager, which is a critical part of my HIL validation process.
Given that I am using the official Starter Kit project downloaded from the Trenz Electronics website, I would expect it to work out-of-the-box.
Warnings
open_hw_manager
connect_hw_server -url localhost:3121 -allow_non_jtag
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3414] Connected to existing cs_server.
current_hw_target [get_hw_targets */xilinx_tcf/Digilent/2516330095A8A]
set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/2516330095A8A]
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/2516330095A8A
current_hw_device [get_hw_devices xczu15_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xczu15_0] 0]
INFO: [Labtools 27-1435] Device xczu15 (JTAG device index = 0) is not programmed (DONE status = 0).
current_hw_device [get_hw_devices arm_dap_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices arm_dap_1] 0]
current_hw_device [get_hw_devices xczu15_0]
reset_run impl_1 -prev_step
launch_runs impl_1 -to_step write_bitstream -jobs 14
[Wed May 21 11:33:39 2025] Launched impl_1...
Run output will be captured here: C:/Users/c/Documents/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/runme.log
set_property PROBES.FILE {C:/Users/c/MasterThesis/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/zusys_wrapper.ltx} [get_hw_devices xczu15_0]
set_property FULL_PROBES.FILE {C:/Users/c/Documents/MasterThesis/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/zusys_wrapper.ltx} [get_hw_devices xczu15_0]
set_property PROGRAM.FILE {C:/Users/c/Documents/MasterThesis/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/zusys_wrapper.bit} [get_hw_devices xczu15_0]
program_hw_devices [get_hw_devices xczu15_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xczu15_0] 0]
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xczu15 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'zusys_i/RGPIO/vio_rgpio' at location 'uuid_C549B3912D39530092A42F2FFB5AA883' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'zusys_i/vio_general' at location 'uuid_EB3ABBC93C055478BA1800E59EB82FB2' from probes file, since it cannot be found on the programmed device.
Has anyone faced this issue when using the official Starter Kit project from Trenz Electronics?
Is there a known fix or additional configuration required for proper VIO detection on the TE0808 board?
I'm attaching the block design diagram for reference.
Any help would be highly appreciated!
Thanks in advance!
,I'm facing an issue with the TE0808-05-BBE81-E board (Zynq UltraScale+ XCZU15EG-1FFVC900E, 4GB DDR4) and I would appreciate any help or guidance.
System configuration:
Board: TE0808-05-BBE81-E
Processor: Xilinx Zynq UltraScale+ XCZU15EG-1FFVC900E
Memory: 4 GB DDR4 SDRAM
Development environment: Vivado 2022.1
Workflow followed:
1-I downloaded the Starter Kit project for the TE0808 from the official Trenz Electronics website and imported it into Vivado.
2-Connected to the hardware using:
3-open_hw_manager
4-connect_hw_server -url localhost:3121 -allow_non_jtag
5-Detected the device with get_hw_devices xczu15_0
6-Generated the bitstream (zusys_wrapper.bit) and .ltx file (zusys_wrapper.ltx) through the implementation (impl_1)
7-Programmed the device using program_hw_devices
Main issue:
Although the bitstream is successfully loaded (DONE status = 1), Vivado does not detect the VIO visualization cores—specifically the vio_general core. As a result, I am unable to visualize any signals in the Hardware Manager, which is a critical part of my HIL validation process.
Given that I am using the official Starter Kit project downloaded from the Trenz Electronics website, I would expect it to work out-of-the-box.
Warnings
open_hw_manager
connect_hw_server -url localhost:3121 -allow_non_jtag
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3414] Connected to existing cs_server.
current_hw_target [get_hw_targets */xilinx_tcf/Digilent/2516330095A8A]
set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/2516330095A8A]
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/2516330095A8A
current_hw_device [get_hw_devices xczu15_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xczu15_0] 0]
INFO: [Labtools 27-1435] Device xczu15 (JTAG device index = 0) is not programmed (DONE status = 0).
current_hw_device [get_hw_devices arm_dap_1]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices arm_dap_1] 0]
current_hw_device [get_hw_devices xczu15_0]
reset_run impl_1 -prev_step
launch_runs impl_1 -to_step write_bitstream -jobs 14
[Wed May 21 11:33:39 2025] Launched impl_1...
Run output will be captured here: C:/Users/c/Documents/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/runme.log
set_property PROBES.FILE {C:/Users/c/MasterThesis/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/zusys_wrapper.ltx} [get_hw_devices xczu15_0]
set_property FULL_PROBES.FILE {C:/Users/c/Documents/MasterThesis/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/zusys_wrapper.ltx} [get_hw_devices xczu15_0]
set_property PROGRAM.FILE {C:/Users/c/Documents/MasterThesis/StarterKitMain/StarterKit/vivado/StarterKit.runs/impl_1/zusys_wrapper.bit} [get_hw_devices xczu15_0]
program_hw_devices [get_hw_devices xczu15_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
refresh_hw_device [lindex [get_hw_devices xczu15_0] 0]
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xczu15 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'zusys_i/RGPIO/vio_rgpio' at location 'uuid_C549B3912D39530092A42F2FFB5AA883' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'zusys_i/vio_general' at location 'uuid_EB3ABBC93C055478BA1800E59EB82FB2' from probes file, since it cannot be found on the programmed device.
Has anyone faced this issue when using the official Starter Kit project from Trenz Electronics?
Is there a known fix or additional configuration required for proper VIO detection on the TE0808 board?
I'm attaching the block design diagram for reference.
Any help would be highly appreciated!
Thanks in advance!
#23
Trenz Electronic FPGA Modules / sys_clk IOSTANDARD for TE0714
Last post by bggardner - May 28, 2025, 04:32:29 PMAccording to SCH-TE0714-04-42I-7-B.PDF, the 25MHz oscillator (U8) is powered by 1.8V. The oscillator output is connected to B14_L13_P on Bank 14 (sys_clk in the board file), which is powered by VCCIO_0. R21 connects VCCIO_0 to 3.3V, thereby making the IOSTANDARD for Bank 14 LVCMOS33. However, LVCMOSS33 requires a minimum input-high voltage of 2.000V per AMD DS181, which the 1.8V-driven oscillator is unable to supply. The TE0714_35_2I board file specifies sys_clk having IOSTANDARD LVCMOS33. Is this an error with the schematic or otherwise unintended?
#24
UltraScale / Re: First "Hello World" - JTAG...
Last post by Ivan7681 - May 28, 2025, 12:54:08 PMHi Meik,
Please try downloading and installing the latest USB to JTAG converter driver from the manufacturer's website:
https://ftdichip.com/products/ft2232h-56q/
This may help resolve the JTAG-related issues you're experiencing.
Please try downloading and installing the latest USB to JTAG converter driver from the manufacturer's website:
https://ftdichip.com/products/ft2232h-56q/
This may help resolve the JTAG-related issues you're experiencing.
#25
UltraScale / Re: First "Hello World" - JTAG...
Last post by Antti Lukats - May 28, 2025, 12:39:05 PMI can no see your screenshots, but at least your DIP switch settings are correct.
Did you try to access the JTAG chain with Vivado Hardware manager? Did it see the JTAG chain?
Did you try to access the JTAG chain with Vivado Hardware manager? Did it see the JTAG chain?
#26
MAX1000 community projects / Re: MAX1000 SDRAM chip
Last post by BR - May 27, 2025, 04:18:13 PMProblem indeed, anyways...
A lot of space on a MAX1000 board for a larger package and placing of those caps a little further from the chip.
Couldn't find another compatible high density sdram memory alternative in 8x8mm package.
Thanks for answering!
A lot of space on a MAX1000 board for a larger package and placing of those caps a little further from the chip.
Couldn't find another compatible high density sdram memory alternative in 8x8mm package.
Thanks for answering!
#27
UltraScale / First "Hello World" - JTAG err...
Last post by Meik - May 27, 2025, 12:54:28 PMHello,
we use a TE07005-04 connected with TE0820 for some first tests regarding MPSoCs and
try to run "Hello World" from the example project "TE0820-te0820-rd-vivado_2024.2-build_1_20250214171345".
Programming over JTAG we got some problems:
Vitis 2024.2 and Vitis Classic 2024.2 (Windows 11) shows the same problems. We connected PC-USB to Mini USB J7, set switches S4 (all to off) and S3 (1, 2, 4 to off; 3 to on).
Running debug "Launch hardware(Single Application Debug" we got following error message: jtag_err (appendix 1)
XSCT Console shows: info_XSCT_Console (appendix 2)
Clicking "Yes" shows: Running_Cortex (appendix 3)
Launching Debugger runs, shows message: FSBL_err (appendix 4) and ends with: Error_while_launching (appendix 5)
We never saw "Hello World". Do you see our Problem? What should we do?
With kindly regards,
Meik Hilse
we use a TE07005-04 connected with TE0820 for some first tests regarding MPSoCs and
try to run "Hello World" from the example project "TE0820-te0820-rd-vivado_2024.2-build_1_20250214171345".
Programming over JTAG we got some problems:
Vitis 2024.2 and Vitis Classic 2024.2 (Windows 11) shows the same problems. We connected PC-USB to Mini USB J7, set switches S4 (all to off) and S3 (1, 2, 4 to off; 3 to on).
Running debug "Launch hardware(Single Application Debug" we got following error message: jtag_err (appendix 1)
XSCT Console shows: info_XSCT_Console (appendix 2)
Clicking "Yes" shows: Running_Cortex (appendix 3)
Launching Debugger runs, shows message: FSBL_err (appendix 4) and ends with: Error_while_launching (appendix 5)
We never saw "Hello World". Do you see our Problem? What should we do?
With kindly regards,
Meik Hilse
#28
MAX1000 community projects / Re: MAX1000 SDRAM chip
Last post by Antti Lukats - May 26, 2025, 08:58:20 AMouch, I did not check the package size!
yes it is a problem!
yes it is a problem!
#29
Arrow USB Programmer2 / USB Blaster III Compatibility
Last post by Antti Lukats - May 23, 2025, 01:44:17 PMHi
starting from Quartus 25.1 it is possible to use FT2232H based JTAG programmers, like our Arrow USB Programmer without the Arrow DLL installation, it is all included nativly with Quartus both for Windows as for Linux.
To enable the UB3 mode you need to modify the FTDI EEPROM contact for UB3 compatible VID/PID.
Note #1: when once programmed to UB3 mode FT_PROG can no longer access the EEPROM, so you can not change back. But there are Linux tools you can use to erase the EEPROM.
Mote #2: the activity LED on Arrow USB Programmer stops working in UB3 mode with the current PCB versions TEI0004-02. In next PCB revision we will change the LED to support UB3 mode.
starting from Quartus 25.1 it is possible to use FT2232H based JTAG programmers, like our Arrow USB Programmer without the Arrow DLL installation, it is all included nativly with Quartus both for Windows as for Linux.
To enable the UB3 mode you need to modify the FTDI EEPROM contact for UB3 compatible VID/PID.
Note #1: when once programmed to UB3 mode FT_PROG can no longer access the EEPROM, so you can not change back. But there are Linux tools you can use to erase the EEPROM.
Mote #2: the activity LED on Arrow USB Programmer stops working in UB3 mode with the current PCB versions TEI0004-02. In next PCB revision we will change the LED to support UB3 mode.
#30
Trenz Electronic FPGA Modules / Re: Random character printed v...
Last post by Antti Lukats - May 23, 2025, 01:35:02 PMrandom characters may appera when the level shifting CPLD IO bank on TE0790 is not powered. This is controlled with dip.3