Recent posts

#11

Trenz Electronic FPGA Modules / Re: TE0701 / TE0711 UART Pins

Last post by Antti Lukats - June 05, 2025, 10:16:45 AM

Hi,
all you need is to read the TE0701 TRM, it is all explained there:

https://wiki.trenz-electronic.de/display/PD/TE0701+TRM

There is a diagram that shows that the CPLD is "forwarding" the UART pins, and a bit later is defined to WHAT pins the forwarding is done. So all the information you need is there.

#12

Trenz Electronic FPGA Modules / TE0701 / TE0711 UART Pins

Last post by haraldmz - June 05, 2025, 09:52:12 AM

Where do I find which pins on JB1 the UART lines are connected to? The TE0701 TRM chap. 5.2 says "UART RX", "UART TX" on JB1, but such pin names do not exist on TE0701 JB1. I tried to get a clue from reading the schematics but the trace ends at CLPD BDBUS0 and 1 (which _may_ be the correct pins but the TRM chap. 6.2 does not state this clearly). But the BDBUS pins aren't available on JB1 anyway.

So what gives?

#13

UltraScale / TE0865-02+TEBT0865+KK0865

Last post by mer - June 04, 2025, 11:42:27 PM

Hello, beginning to put together as system utilizing TE0865-02+TEBT0865+KK0865. Noticing that the TEBT0865 TRM is empty. Am I looking in the wrong place? https://wiki.trenz-electronic.de/display/PD/TEBT0865
Also, there doesn't seem to be an obvious place to plug in the KK0865 pwm fan. Little help?

#14

UltraScale / Re: Support Request for TE0808...

Last post by JH - June 02, 2025, 08:50:31 AM

Hi,
bitstream itself does not configure PS. This will be done by FSBL, not with bitstream.This is the reason why you didn't see any VIO core, because CLK is missing. In case you want to use PS-PL CLKs and you need only PL part, boot system with your configured PS from SD Card (You can use our prebuilt Boot.bin in case you use the same CLKs like we in our reference design) and overwrite PL over JTAG like you has done above.
br
John

#15

Trenz Electronic FPGA Modules / Re: sys_clk IOSTANDARD for TE0...

Last post by bggardner - May 30, 2025, 05:45:23 PM

Thank you.  The sys_clk input (somehow) still works using LVCMOS33, but also works with your suggested changes.  For the benefit of others, I replaced

set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports sys_clk]

with

set_property INTERNAL_VREF 0.9 [get_iobanks 14]
set_property -dict {PACKAGE_PIN T14 IOSTANDARD SSTL18_I} [get_ports sys_clk]

#16

Trenz Electronic FPGA Modules / Re: sys_clk IOSTANDARD for TE0...

Last post by Antti Lukats - May 30, 2025, 12:07:53 PM

It is documentation XDC issue, please select SSTL18_I as IO Standard, after that you need open device constraints windows and use mouse to drop the IO Bank 14 to "0.9V" this will enable internal VREF.

Then it should work.

#17

UltraScale / Re: First "Hello World" - JTAG...

Last post by Antti Lukats - May 30, 2025, 11:32:07 AM

Hi Meik,

Please try downloading and installing the latest USB to JTAG converter driver from the manufacturer's website:

https://ftdichip.com/products/ft2232h-56q/

This may help resolve the JTAG-related issues you're experiencing.

I do not think that the issue is related to FTDI drivers. The JTAG seems to work OK.

#18

UltraScale / Re: Support Request for TE0808...

Last post by Antti Lukats - May 30, 2025, 11:30:36 AM

your report already says what the likely issue is, namly if the VIO core does not see a free running clock, it will not be detected. So it is a clocking issue.

#19

Trenz Electronic FPGA Modules / Re: Help Needed: Best Starter ...

Last post by Antti Lukats - May 30, 2025, 09:15:38 AM

The BEST is that you use our preferred method and download our reference design. You should use 2023.2 version. So you need update your Vivado. We have no support for 2023.1

PMOD is just 8 IO, what Advice you need about working with 8 IO pins?

Same for Clock, what advice are you looking? There are some options in the PS config in Vivado, and you can use PLL in the fabric to generate more clocks as needed.

#20

Trenz Electronic FPGA Modules / Help Needed: Best Starter Setu...

Last post by davidmillerdavid - May 29, 2025, 07:23:52 AM

Hi everyone,

I am fairly new to working with Trenz boards and recently got the TE0715-04-30-2C module. I am planning to use it with Vivado 2023.1 on a Windows 11 setup. I have been through the Trenz Wiki but wanted to ask directly here :-

What is the recommended starting point in terms of reference designs or precompiled projects for this board: ??

Do I need to customize the board files for Vivado 2023.1 or are the default ones on GitHub still good to go: ??

Any advice on working with the PMOD interfaces or clock config on this module: ??

Would really appreciate input from anyone who has hands-on experience with this board. Just want to make sure I am starting off with the right setup and avoid rookie mistakes.

Thanks in advance!!

With Regards,
David

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