Trenz Electronic GmbH Support Forum

Open Source => Open source hardware => Topic started by: toshas on March 27, 2018, 08:32:52 AM

Title: TE0723-02(03) vs TE0723-01
Post by: toshas on March 27, 2018, 08:32:52 AM
Hi!

I would ask you about changes in TE0723.
I'm able to find difference between -02 and -03.
But differences between -01 and -02 isn't described.
At least I can see that type and routing style of DDR memory was changed.
Was it part availability issues/performance issues or signal integrity problems ?
Will you share AD project for TE0723-03 as it was for TE0722 ?

Thanks a lot!


P.S. I would like to say many thanks to Antti Lukats, who made excellent projects and shared it to public.
I'm using these projects as "education book" of implementing design with Zynq.
No one except him provide schematic and pcb layout for Zynq project with DDR memory. It is very exciting!
I hope that him continue to create cool open projects in future.
Title: Re: TE0723-02(03) vs TE0723-01
Post by: Antti Lukats on March 28, 2018, 11:31:28 AM
Hi

this is easy to explain and well a SAD STORY.

There used to be one SUPER COOL LPDDR2 IC, 16 bit bus small package. optimal for all low cost small and simple Zynq stuff. We designed this IC into many designs as Micron promised it will be available. We could by one tray.. and then

Micron is still looking for PCN (product change notice) for this product - the just forgot to tell us they are stopping this one and only good LPDDR2 device from production.

So in REV-2 there is DDR3 ..

Thats the story

Antti
Title: Re: TE0723-02(03) vs TE0723-01
Post by: toshas on March 29, 2018, 07:55:57 AM
Hi!

Thanks! It's really a sad story..

What do you think about DDR2 ? Looks like its good alternative to LPDDR2 ?
It's available up to 256MB, 0.8 pitch case, termination is optional if 1 chip is used and chips are placed close together. It's also supported by 7series (MIG ans PS).

By the way could you please explain some details about LPDDR2 routing in REV1 ? As I can see both data byte lanes are routed on different layers (top/bot) and lenght match does not exist (~4-5mm difference). Do you perform any kind of simulation for routing verification ? Does any performance problem exist ? Because I see also that in REV2 these things were changed and leght match is exist.

Could you share layout in pdf format and net lenght as separate file, if it's impossible to share entire AD REV2/3 project as opensource ?

Thanks again!