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Trenz Electronic Products => Trenz Electronic FPGA Modules => Topic started by: jcuellar on February 22, 2018, 08:18:39 PM

Title: TE0820 on a TE0703 board - Getting started
Post by: jcuellar on February 22, 2018, 08:18:39 PM
Hello,
I recently received a TE0820-02-02CG-1EA board along with the TE0703 carrier board and I'm trying to get them running.

I'm using Vivado 2017.4 as recommended with the reference design:  /TE0820/Reference_Design/2017.4/test_board/TE0820-test_board-vivado_2017.4-build_06_20180206203359.zip
First I tried using the configuration files in the "prebuilt" directory and I get the following warnings:

INFO: [Labtools 27-1434] Device xczu2 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'zusys_i/vio_0' from probes file, since it cannot be found on the programmed device.

I then tried rebuilding the design and inserting an ILA in the design but I receive the same/similar warnings:

INFO: [Labtools 27-1434] Device xczu2 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'u_ila_0' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'zusys_i/vio_0' from probes file, since it cannot be found on the programmed device.

Along with the above hardware, I also purchased a TE0713-01-200-2C board along with a second TE0703 carrier board. This second system works as expected. I was able to build the TE0713 reference design with the recommended 2016.4 Vivado and insert a debug core. This debug core is detected, and can be armed and triggered.

All jumpers and switches are at factory settings. Any help is greatly appreciated. Thank you.
Title: Re: TE0820 on a TE0703 board - Getting started
Post by: JH on March 05, 2018, 08:54:36 AM
Hi,

did you program bitfile only? With Bitfile only the Zynq PS is not initialized, so no PS-PL CLK  is available and also no debug core, which used this clks. Please follow instructions from:

br
John