Recent posts

#1

Trenz Electronic FPGA Modules / Re: TE0720-04-61C33MA: ps7_ini...

Last post by Keisuke Sakai - September 01, 2026, 11:04:52 AM

Additional information:

I also tested the same TE0720 module with a TEBA0841-02 carrier board.

On the TEBA0841-02, ps7_init completes without any errors and the values of 0xF8000B40 and 0xF8000B44 change from 0x00000800 to 0x00000600, similarly to the behavior observed on the TE0703.

However, DDR still cannot be accessed afterwards:

--------------------------------------------------
On TEBA0841-02 (Failing)
--------------------------------------------------

mrd 0xF8000B40
F8000B40: 00000800

mrd 0xF8000B44
F8000B44: 00000800

mrd 0x00100000
Memory read error at 0x100000.
Cannot access DDR: the controller is held in reset

source {ps7_init.tcl}

ps7_init

mrd 0xF8000B40
F8000B40: 00000600

mrd 0xF8000B44
F8000B44: 00000600

mrd 0x00100000
Memory read error at 0x100000.
Cannot access DDR: the controller is held in reset

--------------------------------------------------

Therefore, there appear to be three different behaviors:

1. TE0703:
   - ps7_init succeeds
   - DDR becomes accessible

2. TEBA0841-02:
   - ps7_init succeeds
   - DDR remains inaccessible

3. Custom carrier:
   - ps7_init itself fails with
     "Invalid DAP IDCODE 00000000"

Since TEBA0841-02 is essentially a power-supply carrier, it seems possible that some boot-stage initialization (for example FSBL-related initialization) is not being executed. Could this explain why DDR remains in reset even though ps7_init completes successfully?

Kind regards,
K. Sakai

#2

Trenz Electronic FPGA Modules / Re: TE0950-03-EGBE21C – Not De...

Last post by YakameinTakashi - August 27, 2026, 03:44:15 AM

Hi Ivan,

Greetings.

I sent an email to support@trenz-electronic.de on August 18, but I have not received a response yet.

Could you please help follow up with them or ping the team on my behalf?

Thank you for your assistance.

Kind regards,

Takashi

#3

Trenz Electronic FPGA Modules / TE0820-04: custom Vivado desig...

Last post by mattcowell - August 26, 2026, 11:16:19 AM

Hi everyone, I'm working with a TE0820-05-4AE21FA module on a TE0706-06 carrier board using Vivado/Vitis 2024.2. The original Trenz reference design boots correctly from a FAT32 SD card and gives the expected UART output, but after creating a small custom Vivado design with the Zynq UltraScale+ PS and an AXI GPIO peripheral, my new BOOT.bin behaves differently. I generated the XSA, FSBL, PMU firmware, bitstream and application from the new design and placed them in the boot image, but although the FSBL initialization messages appear over UART, the PL does not seem to be programmed correctly and I cannot reliably access the AXI GPIO from Vivado Hardware Manager. I have compared the PS and DDR configuration with the reference project, checked the TE0820 board files and part selection, regenerated the FSBL and PMU firmware, verified the bitstream and implementation, checked the SD formatting and boot-mode switches, and confirmed that restoring the original reference BOOT.bin makes the board work normally again. I'm wondering if there are any TE0820-specific PS, FSBL or boot-image settings that must be preserved when creating a custom design with Vivado 2024.2. Also, is there a recommended way to verify from the UART or Vivado Hardware Manager that the PL bitstream was actually loaded during SD boot? I can provide the Vivado project configuration, XSA, BOOT.bin partition information, UART log and switch settings if those would help troubleshoot the issue.

Basketball Bros

#4

Trenz Electronic FPGA Modules / TE0720-04-61C33MA: ps7_init fa...

Last post by Keisuke Sakai - August 26, 2026, 11:04:26 AM

Hi,

I am using a TE0720-04-61C33MA SOM with Vivado/Vitis 2024.2.
(Using "TE0720-te0720-rd-vivado_2024.2-build_1_20250618151152.zip")

The same SOM, the same hardware design, and the same ps7_init.tcl are tested on:

- TE0703 carrier board (working)
- Custom carrier board via Platform Cable USB II (failing)

JTAG access is working on both boards.

Both ARM Cortex-A9 cores are visible in XSCT and can be stopped successfully. However, DDR memory cannot be accessed on the custom carrier, as shown in the logs below.

-------------------------------------------------------
TE0720 configuration-related pins on my custom carrier:
-------------------------------------------------------

- JTAGMODE (JM1-89): GND
- NOSEQ (JM1-7): GND
- MODE (JM1-32): 3.3 V
- PGOOD (JM1-30): Open
- EN1 (JM1-28): 3.3 V
- MIO0 (JM1-87): Open

--------------------------------------------------
On TE0703 (Working)
--------------------------------------------------

connect
targets
targets -set -filter {name =~ "APU"}
stop
targets -set -filter {name =~ "ARM Cortex-A9 MPCore #0"}

mrd 0xF8000B40
F8000B40: 00000800

mrd 0xF8000B44
F8000B44: 00000800

mrd 0x00100000
Memory read error at 0x100000.
Cannot access DDR: the controller is held in reset

source {C:/TE0720-te0720-rd-vivado_2024.2-build_1_20250618151152/te0720-rd/vivado/vitis/zsys_plat/hw/ps7_init.tcl}

ps7_init

mrd 0xF8000B40
F8000B40: 00000600

mrd 0xF8000B44
F8000B44: 00000600

mrd 0x00100000
100000: F7EFEFFF

--------------------------------------------------
On Custom Carrier (Failing)
--------------------------------------------------

connect
targets
targets -set -filter {name =~ "APU"}
stop
targets -set -filter {name =~ "ARM Cortex-A9 MPCore #0"}

mrd 0xF8000B40
F8000B40: 00000800

mrd 0xF8000B44
F8000B44: 00000800

mrd 0x00100000
Memory read error at 0x100000.
Cannot access DDR: the controller is held in reset

source {C:/TE0720-te0720-rd-vivado_2024.2-build_1_20250618151152/te0720-rd/vivado/vitis/zsys_plat/hw/ps7_init.tcl}

ps7_init

Memory read error at 0xF8000B44.
Invalid DAP IDCODE 00000000.
Invalid DAP ACK value: 0

mrd 0xF8000B40
F8000B40: 00000800

mrd 0xF8000B44
F8000B44: 00000800

mrd 0x00100000
Memory read error at 0x100000.
Cannot access DDR: the controller is held in reset

--------------------------------------------------

The same SOM, the same Vivado/Vitis version, and the same ps7_init.tcl work correctly on the TE0703 carrier board, but ps7_init fails on the custom carrier before DDR initialization completes.

Besides hardware-related causes, are there any software settings, configuration options, or debugging approaches that could help identify or resolve this issue?

Any suggestions for further investigation would be greatly appreciated.

Kind regards,
K. Sakai

#5

Trenz Electronic FPGA Modules / TE0820 upgrading from 2024.2 ...

Last post by keong.ho - August 21, 2026, 03:20:15 AM

Hi

I am currently using Trenz TE0820 with TE0706 carrier cards.
Will there be any upgrade from its Vivado 2024.2 to 2025.2 due to some CVE discovered last year?
If this is in progress, is there an estimated timeline?

regards
Keong

#6

UltraScale / Re: TE0823-02: PG_ALL/XRSTOUT ...

Last post by M.Tserabei - August 18, 2026, 03:28:24 PM

Hallo. Which carrier do you use? Are you sure U4 (BD39040MUF-CE2) VDD = 3.3V? Or RSTIN = 0.85V?
Because RSTIN = 0.85V says that 3.3VIN = 3.5V
Best regards, Maksim Tserabei

#7

UltraScale / TE0823-02: PG_ALL/XRSTOUT stay...

Last post by pratik_chavan - August 17, 2026, 06:30:09 AM

Hello Trenz Team,

I am replacing our existing SoM with TE0823-02-3PIT1MA. The same carrier board and SD boot setup work with our old SoM (with same Zynq UltraScale+ device/part).I have checked the TE0823 schematic and verified that the required power rails are present.

On the TE0823:

All required power rails are present.
PS_REF_CLK = 33.33 MHz
PS_POR_B = 1.8 V
U4 (BD39040MUF-CE2) VDD = 3.3 V
RSTIN = 0.85 V
DIN1–DIN4 ≈ 0.8 V as expected from the resistor dividers
WDEN = 0 V
XRSTOUT (pin 15) = ~0.02 V and stays LOW continuously
PG_ALL = ~0.017 V
No SD clock activity and no UART boot logs.

I have tried both states of the carrier-board boot-mode pin.

Could you please confirm:

1. Can XRSTOUT/PG_ALL remaining LOW prevent the ZynqMP from booting?
2. If all DIN1–DIN4, RSTIN, and VDD are correct, why could U4 still keep XRSTOUT LOW?
3. Does the TE0823 CPLD require PG_ALL to be HIGH before allowing normal ZynqMP startup?

Thanks.

#8

Trenz Electronic FPGA Modules / Re: TE0950-03-EGBE21C – Not De...

Last post by Ivan7681 - July 30, 2026, 09:40:14 AM

Dear Takashi,

Based on the symptoms you described, I think the board is damaged and requires inspection or repair.

Could you please ask the customer to send an email to support@trenz-electronic.de including the board serial number and a description of the issue?

Once we receive this information, we will be able to open an RMA case and proceed with the inspection.

Best regards,

Ivan Grishchenko

#9

Trenz Electronic FPGA Modules / Re: TE0950-03-EGBE21C – Not De...

Last post by YakameinTakashi - July 30, 2026, 02:10:54 AM

Hi Martin,


I received the 2 photos from customer.(I don't know how to attached in here But I could explain)

1. LED photo.
12V on(Green light)
5V on (Green light)
3.3V FMC off (no light)

2. Toggle switch photo
Boot and Toggle is all left side(number side 1.2.3.4)


The customer later said, "I wasn't able to figure out the Versal LED and Artix LED, but basically, all the LEDs are off except for the two green 12V/5V indicator LEDs, which are lit."

Could you give some advice?

Thank you so much.
Kind Regards,
Takashi

#10

Trenz Electronic FPGA Modules / Re: TE0950-03-EGBE21C – Not De...

Last post by YakameinTakashi - July 29, 2026, 06:20:54 AM

Dear Martin,
The serial number is 978849.

I am currently gathering the remaining information requested and will get back to you as soon as possible.
Best regards,
Takashi