Recent posts

#81

EDDP-EDPS Support / Encountered an error while cre...

Last post by ALLEWU - April 15, 2025, 08:37:22 AM

I followed the Quick Start guide and used the FOC template, but when I try to build the project, I get the following error. Does anyone know how to fix it?

#82

Trenz Electronic FPGA Modules / Connecting SFP 2 SMA adapter t...

Last post by rng - April 10, 2025, 03:37:11 PM

Hello,
I'm currently working on the vc709 FPGA and i wanted to connect the highspeed transceiver to an ADC through a SMA cable. Unfortunately the vc709 doesn't have a transceiver connected directly to a SMA output (some boards do have this connection such as the zcu102). I found a SFP to SMA adapter that seems to solve this issue because some of the vc709 transceivers are connected to SFP+ ports. My question is: the adapter says "SFP 2 SMA" and not "SFP+ 2 SMA", will it work on the SFP+ port of the vc709 board? If yes, will there be downsides such as lower speed?

Thank you for your time.

Marco

#83

Trenz Electronic FPGA Modules / Recommendation for small FPGA ...

Last post by rsalasidis - April 06, 2025, 12:11:20 AM

The goal is to read and average a multi channel high speed ADC.

I need a small FPGA module that would need to have 3 serial inputs channels (about 40 MHz serial frequency each channel). ? 3 x 32 bit long shift registers.

Each channel is a 24 bit value, sent in a 32 bit frame

Add 256 consecutive integer reads and then send the values x 3 via SPI to a slave SPI device.

The adding cells are then cleared and the process repeats

Would the MAX1000 module work for the above, or would you recommend some other low cost module?

Thanks for any suggestions

#84

MAX1000 community projects / Re: Playing ZX Spectrum in HDM...

Last post by Subcritical - April 05, 2025, 12:57:06 PM

Let's work on the fantastic.
Let's compile for MAX1000.

Let's see what I show for LEDs 0 through 7:
assign LEDS[0]=tested1; //alternate sound every second
assign LEDS[1]=tested2;
assign LEDS[2]=timed; //if a ghost hits, it will time out for one second
assign LEDS[3]=timed; //if a ghost hits, it will time out for one second
assign LEDS[4]=rebote[0]; //bounce on the right and left margins.
assign LEDS[5]=rebote[0]; //bounce on the right and left margins.
assign LEDS[6]=rebote[1];//bounce on the top or bottom margin
assign LEDS[7]=rebote[1];//bounce on the top or bottom margin

In the RTL, we see where the audio data is located.

We proceed to add an HDMI converter to Professor Miguel Angel Rodriguez Jodar's fantastic project at 640x480 and a refresh rate of 60Hz, approximating the pixel clock to 25.2MHz.
https://www.us.es/trabaja-en-la-us/directorio/miguel-angel-rodriguez-jodar

These original sources can be found at:
http://www.forofpga.es/viewtopic.php?f=32&t=40&p=118#p118

Also, when the ghost bounces, it has been removed when it does so with the top and bottom margins and assigns it to a row.
And when it does this with the sides, it assigns it to a column bounce.
By making a logical or between both bounce signals, we have the bounce to calculate with a timer so that the bounce sounds.

I reuse some sounds from other exercises.
These sounds are 8-bit.
The sound lasts 2 seconds since they alternate from the right speaker for 1 second to the left for another second.
If the timing were with the parameter:
parameter CYCLES_2S=14000000;
we move on to:
parameter CYCLES_2S=28000000;

We would see the sound alternating between the left and right speakers when the sound completes after 2 seconds.

I'm uploading this exercise because I'll be using a higher-resolution HDMI file later,
and I have the sound in 8-bit, and I'd like it to be in 16-bit.

#85

MAX1000 community projects / Re: Playing ZX Spectrum in HDM...

Last post by Subcritical - April 01, 2025, 07:01:49 PM

Counter at 1280x720, in which virtual LEDs are generated, and the upper octet of the red ones.
They are redirected to the LEDs present on the MAX1000.
The compilation generates these results.

Flow Status Successful - Tue Apr 01 18:25:45 2025
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Revision Name max10_50
Top-level Entity Name hdmi_leds
Family MAX 10
Device 10M08SAU169C8G
Timing Models Final
Total logic elements 358 / 8,064 (4%)
Total registers 219
Total pins 19 / 130 (15%)
Total virtual pins 0
Total memory bits 0 / 387,072 (0%)
Embedded Multiplier 9-bit elements 0 / 48 ( 0 % )
Total PLLs 1/1 (100%)
UFM blocks 0 / 1 ( 0 % )
ADC blocks 0 / 1 ( 0 % )

It's important to note that the number of memory blocks is zero.
To create a display with a MAX 10 SuperCPLD chip, in this case a MAX1000, there is no memory consumption.
Even more importantly, this exercise only consumes 4% of the space of the 10M08SAU169C8G chip.

#86

Trenz Electronic FPGA Modules / TE0703 + TE0820 Boot Issue

Last post by Remi - April 01, 2025, 02:23:27 PM

I am currently working with the TE0703 carrier board and TE0820-04-3BE21MA module, attempting to boot from an SD card.

Steps I have taken so far:

I downloaded the prebuilt ZIP folder from the following link:
Trenz Reference Design 2024.2

Inside the downloaded folder, I navigated to:
prebuilt → boot_images or OS or hardware → 3eg_1e_2Gb (since I have the TE0820-04-3BE21MA).

I copied the necessary boot-related files onto a FAT32 partition on my SD card.

I ensured that the DIP switches were correctly set for SD card boot mode.

I connected the TE0703 to my PC via a Micro-USB to USB cable and opened a serial terminal (PuTTY/Minicom).

Observed Behavior:

No output appears on the serial terminal.

LED D1 and D3 remain red.

LED D2 (green) blinks intermittently instead of staying continuously lit, which I understand should indicate a successful boot.

The Ethernet LEDs are continuously orange, suggesting that the DIP switches are correctly configured.

Is there any step I might have missed? Could you provide any guidance or documentation to help troubleshoot this issue?

Thanks a lot for any helps , ( i'm a beginner in Trenz board )

#87

MAX1000 community projects / Re: Playing ZX Spectrum in HDM...

Last post by Subcritical - March 31, 2025, 12:24:48 PM

Let's move the VT105 pin to the MAX1000 pinout, from the CYC1000 one, step by step.

Original sources:
https://pdp2011.sytse.net/wordpress/pdp-11/

Sources with the first wrapper and for the CYC1000 pinout:
https://github.com/AtlasFPGA/vt105_2023_PDP11/tree/main

First, we check if the description is correct, if it compiles, and if it doesn't generate errors.

We proceed to change the FPGA chip to the SuperCPLD MAX 10 family, i.e., the MAX1000 10M08SAU169C8G.
We compile so that it detects the design signals and then we perform the signal-to-pin assignment one by one from the text file.
We correctly place the corresponding pinout for the MAX1000 pin.

As for the serial port, I'm going to make a crossover, putting TX where RX is, on the ATLAS board.
There are two serial ports; the one I'm going to use as the main one is the one associated with the FTDI FT2232H.

Once compiled, you'll see that there's enough space. This includes both the number of logic elements used, the number of registers, and the block memory "BRAM."

Note that the user flash memory blocks "UFM" and the ports for sampling analog signals "ADC" have not been used.

I open Pin Planner.
I proceed to assign pin to pin.

Let's see if they are really crossed. To do this, go to the ATLAS website and look at the ports associated with the CYC1000 twin board to compare the serial port configuration.

We see the assignments. There are two possibilities for CYC1000 in the VT100 or VT105 terminal configuration: using a serial port directly via pins or using the FT2232H. To switch, uncomment whether you want UART1 and UART2.

We see that they are swapped where RX is, so TX should be placed:
We see that they are swapped where RX2 is, so TX2 should be placed:
#set_location_assignment PIN_R7 -to rx
set_location_assignment PIN_R7 -toTX ##Transmitter output of FT2232H (Tx) 3.3 V - THIS IS SWITCHED TO RX

Then we are doing it correctly by crossing TX with RX for both UART1 and UART2.
Let's adjust the frequencies to more precise ones to see if the VT105 terminal displays.

I disconnect the Max1000 SuperCPLD.
The default description I have for one of the two internally hosted data streams is 24-bit display.

We swapped the HDMI wrapper; the first has less color depth and cannot carry sound.
The one we implemented can carry sound and also has 24-bit support, but only uses almost 2000 logical elements or "kles."

After having several errors, the first one caused comments with // and the second one when assigning signals in the wrapper.
The signals in both wrappers are practically identical, which is the great advantage of using VHDL.

We added the signal-to-pin correspondence.
In TMDS format, from 0 to 7.

We now have a VT105 terminal on the RX and TX ports of the FTDI FT2232H, in my MAX1000.

#88

Trenz Electronic FPGA Modules / te0711 + te0703 Ethernet

Last post by actualengine - March 27, 2025, 06:18:04 PM

I notice that the RJ45 pins on the te0703 route as differential pairs directly to the Artix-7 FPGA on the te0711 (no Phy chip in-between). Can I implement standard ethernet like this? I've only ever seen FPGAs attached to PHYs, never direct connect. Thanks!

#89

MAX1000 community projects / Re: Playing ZX Spectrum in HDM...

Last post by Subcritical - March 25, 2025, 06:21:35 PM

Having already created two different screensaver implementations, we used a VT52 terminal. If you look at the upper left corner, you'll see the seconds. They are slightly faster since, for better visualization in DVI(HDMI, we set a clock of 50.40 MHz, The design uses at first a 50MHz clock as the initial design frequency.

ATLAS Sources:
https://github.com/AtlasFPGA/vt52

Intel/Altera's intellectual properties, such as the phase-locked loop or "PLL," have been approximated to a pixel clock of 25.2 MHz, which gives a resolution of 640x480 with 60Hz vertical synchronization, the exact clock is 25,175Mhz.

You will typically encounter the following errors if you start from a CYCLONE design in families I through IV.
Typically, projects have this configuration:
Single Uncompressed Image (912Kbits UFM)

Let's view the error:
"16031 Current Internal Configuration mode does not support memory initialization or ROM.
Select Internal Configuration mode with ERAM."

This is a memory initialization error.

Now we apply the address and change the parameters.
Assignments - Device - Device and Pin Options - Configuration - Configuration Mode: Single uncompressed image with Memory Initialization
Translate.

The design compilation has been successful.
It is very important that the "IP" intellectual property rights are transferred to the MAX 10 family, given that we have a Max1000 SuperCPLD/FPGA.

Let's begin programming.
And we'll see how the VT52 terminal design shows the seconds of activity in the upper left corner.

I'm slowly translating the comments into other languages.
Greetings.

#90

MAX1000 community projects / Re: Playing ZX Spectrum in HDM...

Last post by Subcritical - March 25, 2025, 01:35:28 PM

We will rename the signals of the implementation, that uses 24bits of color created by Piotr.go.

Code Select Expand

https://github.com/piotr-go/Lichee-Tang/blob/master/VGA/src/vga.v
To the nomenclature in the previous demo/hdmi demo DVI_1280x1024_max1000.

We visualize the files *.qsf.

VGA.QSF signals:

Code Select Expand

set_location_assignment pin_h6 -to SYS_CLK
set_location_assignment pin_h5 -to TMDS [0]
set_location_assignment pin_k10 -to TMDS [1]
set_location_assignment pin_h13 -to TMDS [2]
set_location_assignment pin_j13 -to TMDS [3]
set_location_assignment pin_k11 -to TMDS [4]
set_location_assignment pin_k12 -to TMDS [5]
set_location_assignment pin_j12 -to TMDS [6]
set_location_assignment pin_l12 -to TMDS [7]

Max10_50.qsf signals:

Code Select Expand

set_location_assignment pin_h6 -to clk12Hz
set_location_assignment pin_h5 -to tmds [0]
set_location_assignment pin_k10 -to tmds [1]
set_location_assignment pin_h13 -to tmds [2]
set_location_assignment pin_j13 -to tmds [3]
set_location_assignment pin_k11 -to tmds [4]
set_location_assignment pin_k12 -to tmds [5]
set_location_assignment pin_j12 -to tmds [6]
set_location_assignment pin_l12 -to tmds [7]

I have made the change of TMDS and SYS_CLK to tmds and CLK12MHz names.

Now change the integrated FPGA.
I proceed to eliminate one by one the assignments of the pins, in pin planner.

I do that because, I want to see the name of the signals.
Let's see if Arrow Blaster is detected.
Appears:

Code Select Expand

USB serial Converter A
USB Serial Converter B

Once the first compilation is finished we enter Pin Planner.
And we see if the name of the signals have been changed.

Next, we will go to all the signs and rename them since we have taken the terminology of the DVI_1280x1024_max1000 screen.
And once the assignments have been changed again, we will proceed to send the flow of data to the Max1000.
And see if the capturer shows the screen_exercise of Piotr.go.

As the signals are seen, they have been renamed, and use the same nomenclature as in the previous screen_exercise.
Once the correspondences of the signals and the pins we rebuilt.

Let's take a walk through the VGA.V file

We will send the data flow to the Max1000.

This exercise is very interesting since it shows how starting from a 640x480 VGA signal with a 60Hz vertical sync.
That makes a 25,175 pixel clock, we visualize the screen at full 24 bits colors, with only 8 HDMI pins.

We will visualize the black box of PPL from intel/altera in the Max 10 family.
We start with a clock from 12MHz.
We approximate by PLL limitations the 25,175MHz Pixel Clock frequency at 25,20000000MHz.
HDMI frequency is 5 times the frequency of pixel clock; that is a 126.00000000MHz Clock.
We visualize that in the Used PLL we could still generate three other frequencies C2, C3. and C4.