Recent posts

#41

Trenz Electronic FPGA Modules / Re: Vivado Board File for TE07...

Last post by JH - September 06, 2024, 11:44:58 AM

Hi,

we offer am reference design:
https://wiki.trenz-electronic.de/display/PD/TE0714+Test+Board
Board Files will be installed locally when you create the project with the scripts.
Alternativ options:
https://wiki.trenz-electronic.de/display/PD/Installation
Note AMD Git is at the moment not up to date, so Option 3 or Option 4 is an alternative.

br
John

#42

Trenz Electronic FPGA Modules / Board Files for Vivado 2024.1

Last post by Hans1255 - September 06, 2024, 10:25:22 AM

I'm using the TE0711 and like to install the Board Files.
The installation failed on the AMD/Xilinx version 2024.4.

#43

Trenz Electronic FPGA Modules / Re: Vivado Board File for TE07...

Last post by Muhammad Ali Khan - September 05, 2024, 01:22:42 PM

I managed to find board files for the TE0714 in the Trenz reference design, and manually added the four board folders for the TE0714 variants to Vivado's board repository directory.  I can now successfully select the TE-0714 board file from Vivado 2019.1.

Hello,
I am new to this board as well and would appreciate if you could share how did you manage to to get the board files in more detail.
Thank You.

Regards,
Muhammad Ali Khan.

#44

Trenz Electronic FPGA Modules / Re: How to find out how many I...

Last post by JH - September 03, 2024, 12:38:46 PM

Hi,
sorry for late reply.
On 7 Series FPGA IDDR Logic is available on all HP and HR IOs, see:
https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO
--> See Chapter 2 page 105 and ILOGIC Resources
On U and U+ Zynq it's same for HP and HR IO Banks.
-->See Chapter 2 page 144ff and ISERDES
HD banks haven't this resources.
--> See chapter 3 page 339

HP Banks supports IO Standards with max 1.8V, HR IO Standards up to 3.3V

Unfortunally we haven't so much Trenz Modules with >80 differential HP and/or HR IOs:
TE0865(U+ Zynq) with 126 differential HP IOs on B2B connector
TE0745(7 Series Zynq) with 72 diff. HP and 48 diff. HR IOs on B2B connector
For modules you need also a carrier, but we haven't a carrier for all of them where all IOs are available on some breakout connector like fmc.

Motherboard
TEB0911 with 96 diff HP on different FMC connectors

br
John

#45

CYC1000 community projects / Re: I present a comunity of IN...

Last post by Subcritical - August 22, 2024, 11:49:41 AM

Core Next186 a clone i80186 that has 80Mips with MPU401 this port belongs to @distwave81. In these videos The Raspberry PI act as a synthesizer.

In This vídeo the Netx186 plays Monkey Island:

In This vídeo the Next186 plays Cool Spot:

In This video the Next186 plays Wing Commander:

Some benchmarcks of Next186:

Sources:
https://github.com/AtlasFPGA/Next186_SoC

#46

Trenz Electronic FPGA Modules / Re: Problem about TE0720

Last post by JH - August 22, 2024, 08:56:55 AM

Hi,
you can change boot mode from QSPI to SD or with newer cpld firmware and compatible carrier to JTAG only.
https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-BootMode
PGOOD Pin as second boot mode pin is available since July 2022, in case you has an older module, than firmware update is needed. If you can't control PGOOD pin depends on your carrier, than you can change boot mode via software: write 0x9100 to register 12 : https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-U-boot
-->  mii write  0x1A 0x0C 0x9100
This reboots zynq in JTAG only mode(as long as you didn't power of the module) and you can erase flash with vivado or vivado labtools (it's like programming you must only deselect programming and verification part).
 
br
John

#47

Trenz Electronic FPGA Modules / Problem about TE0720

Last post by violetbeth - August 22, 2024, 08:37:11 AM

Hello,

I'm having an issue with the TE0720 board. I think I may have accidentally programmed the QSPI with U-Boot at some point. Since then, every time I try to run a test app from Vitis, U-Boot launches instead. It occasionally runs my test app, but most of the time it fails.

#48

EDDP-EDPS Support / Re: unable to boot TE0950 with...

Last post by JH - August 20, 2024, 08:48:45 AM

Hi,
did you also put the Boot.bin file on the SD card?
https://wiki.trenz-electronic.de/display/PD/TE0950+Test+Board#TE0950TestBoard-SD-Bootmode
it's \prebuilt\boot_images\23_1lse_8gb\u-boot\Boot.bin for the most assembly variants
br
John

#49

Trenz Electronic FPGA Modules / Re: TE0706-03 Carrier Card wit...

Last post by JH - August 20, 2024, 08:42:17 AM

Hi,
we have some reference design also with "Hello World" baremetal example instead of petalinux:
https://wiki.trenz-electronic.de/display/PD/TE0715+Test+Board
br
John

#50

UltraScale / Re: Accessing UART1 on zynqmp ...

Last post by JH - August 20, 2024, 08:36:44 AM

Hi,
uart1 is default not activate on our board files with basic PS configuration and also not routed to any IO.
There are some free MIO available which goes to the CPLD and can be forwarded to J35 XMOD, which you can use for UART1. You must do following:
Enable UART1 on your PS with MIO36/37
Change CPLD Firmware to forward this MIO to J35 XMOD and update CPLD firmware with your custom firmware:
https://wiki.trenz-electronic.de/display/PD/SC0911+CPLD
You must connect this Pins inside the CPLD
MIO36--> CPLD G7 --> CPLD C17 --> J35 XMOD A
MIO37<-- CPLD D14 <-- CPLD B19 <-- J35 XMOD B
CPLD Source Code: https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Motherboards_and_Carriers/TEB0911/REV04/Firmware
Update instructions: https://wiki.trenz-electronic.de/display/PD/TEB0911+CPLD+Firmware

br
John