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#1
Trenz Electronic FPGA Modules / Re: hdl coder settings for the...
Last post by Herminiaitsch - Today at 06:04:10 AMQuote from: Herminiaitsch on Today at 05:58:09 AMSo you see one of the main effects is when you change the frequency.What can I change other than changing your first wrong action?
#2
Trenz Electronic FPGA Modules / Re: hdl coder settings for the...
Last post by Herminiaitsch - Today at 05:58:09 AMQuote from: Joni98 on July 16, 2025, 09:50:47 AMHello,So you see one of the main effects is when you change the frequency.
I want to create an IP core using the HDL coder in MATLAB Simulink. It's working so far. When I create the IP core, my outputs switch at a different frequency than in the MATLAB simulation. Depending on the settings I use, I'm sometimes closer to the simulation or further away. However, I haven't been able to find the exact frequency after experimenting. I've used the following settings see in the pictures. Are there any "reference settings" for this, or what parameters could be causing the problem? The CLK for the IP core in Vivado is set to 250 MHz (same as the settings in MATLAB). The Simulink model is divided into an embedded C part and an FPGA part. The settings for the C part shouldn't play a role in the IP core generation? Can anyone help, or has anyone already done this?.
#3
Trenz Electronic FPGA Modules / Flash/SD booting TE0706+TE0720...
Last post by trondeaa - Today at 12:01:29 AMI am struggling to make boot mechanism to work.
We are using a combination of TE0706-04-A and TE0720-04-61Q33MA.
For design entry we are using VITIS/VIVADO 2025.1
Entering a simple design with bare metal works fine and the Hello world example is working without problems.
We have made a very small application toggling one I/O-pin
When we build the bootfile we are able to program the flash if the board is in SD boot mode.
BUT:
It refuses to boot when set to FLASH boot mode (after flash has been programmed).
It also refuses to boot with a SD card programmed with boot.bin and set to SD boot mode.
The FPGA is not programmed in any of these two cases.
By accident we discovered that the system was able to boot if an identical boot.bin was programmed to flash, and the same file stored on the SD card, while the board was set to flash boot (S1-3 to off).
In this case the system did boot, the FPGA was programmed and the application started.
(We tried to change details in the application, ran the program and reprogrammed the FLASH)
After reboot the application changed back to the unmodified one.
This indicates that the boot sequence fetches the application from SD.
We have not tried to find out where the bitfile for the FPGA is fetched (FLASH or SD).
We are using a combination of TE0706-04-A and TE0720-04-61Q33MA.
For design entry we are using VITIS/VIVADO 2025.1
Entering a simple design with bare metal works fine and the Hello world example is working without problems.
We have made a very small application toggling one I/O-pin
When we build the bootfile we are able to program the flash if the board is in SD boot mode.
BUT:
It refuses to boot when set to FLASH boot mode (after flash has been programmed).
It also refuses to boot with a SD card programmed with boot.bin and set to SD boot mode.
The FPGA is not programmed in any of these two cases.
By accident we discovered that the system was able to boot if an identical boot.bin was programmed to flash, and the same file stored on the SD card, while the board was set to flash boot (S1-3 to off).
In this case the system did boot, the FPGA was programmed and the application started.
(We tried to change details in the application, ran the program and reprogrammed the FLASH)
After reboot the application changed back to the unmodified one.
This indicates that the boot sequence fetches the application from SD.
We have not tried to find out where the bitfile for the FPGA is fetched (FLASH or SD).
#4
Trenz Electronic FPGA Modules / Re: hdl coder settings for the...
Last post by Martin R. - July 16, 2025, 02:48:18 PMHi,
our experience with MatLab/Simulink is very limited. If you think it is a problem of the settings MatLab/Simulink support should be your fist choice.
I can give only very general advice like: Check design clock source frequencies in hardware compared to simulation.
our experience with MatLab/Simulink is very limited. If you think it is a problem of the settings MatLab/Simulink support should be your fist choice.
I can give only very general advice like: Check design clock source frequencies in hardware compared to simulation.
#5
Trenz Electronic FPGA Modules / hdl coder settings for the te0...
Last post by Joni98 - July 16, 2025, 09:50:47 AMHello,
I want to create an IP core using the HDL coder in MATLAB Simulink. It's working so far. When I create the IP core, my outputs switch at a different frequency than in the MATLAB simulation. Depending on the settings I use, I'm sometimes closer to the simulation or further away. However, I haven't been able to find the exact frequency after experimenting. I've used the following settings see in the pictures. Are there any "reference settings" for this, or what parameters could be causing the problem? The CLK for the IP core in Vivado is set to 250 MHz (same as the settings in MATLAB). The Simulink model is divided into an embedded C part and an FPGA part. The settings for the C part shouldn't play a role in the IP core generation? Can anyone help, or has anyone already done this?.
I want to create an IP core using the HDL coder in MATLAB Simulink. It's working so far. When I create the IP core, my outputs switch at a different frequency than in the MATLAB simulation. Depending on the settings I use, I'm sometimes closer to the simulation or further away. However, I haven't been able to find the exact frequency after experimenting. I've used the following settings see in the pictures. Are there any "reference settings" for this, or what parameters could be causing the problem? The CLK for the IP core in Vivado is set to 250 MHz (same as the settings in MATLAB). The Simulink model is divided into an embedded C part and an FPGA part. The settings for the C part shouldn't play a role in the IP core generation? Can anyone help, or has anyone already done this?
#6
MAX1000 community projects / Re: Playing ZX Spectrum in HDM...
Last post by Subcritical - July 14, 2025, 08:27:15 PMThe well-known game of life in FPGA format has used the available sources from the platform:
https://github.com/marsohod4you/FPGA_game_lifeSince
This could be seen here.
The max1000 only has 8kles, so the size of the board where the game is played, is a quarter of the total, that can be displayed on the screen.
FPGA_game_life-max1000.zip
https://github.com/marsohod4you/FPGA_game_lifeSince
This could be seen here.
The max1000 only has 8kles, so the size of the board where the game is played, is a quarter of the total, that can be displayed on the screen.
FPGA_game_life-max1000.zip
#7
Trenz Electronic FPGA Modules / Re: Andromeda PHY not detected
Last post by akarcher - July 07, 2025, 11:36:42 PMI did resolve this: The implementation of the level shifters for the LEDs was flawed on my base board, and this causes a change in the PHY address. I was unaware that the LEDs and PHY address were related at all.
#8
Trenz Electronic FPGA Modules / Andromeda PHY not detected
Last post by akarcher - July 03, 2025, 02:25:42 AMI am using the prebuilt reference design files on AM0010-02-4DE21MA.
Board does boot, but I do not see ethernet. Since the Phy is on the module I don't think this can be an issue with baseboard I built. I did copy the AMB0010 for Ethernet, USB and SD card.
from U-boot:
ZynqMP> net list
Could not get PHY for eth0: addr 3
Could not get PHY for eth0: addr 3
eth0 : ethernet@ff0e0000 00:00:00:00:00:00
Board does boot, but I do not see ethernet. Since the Phy is on the module I don't think this can be an issue with baseboard I built. I did copy the AMB0010 for Ethernet, USB and SD card.
from U-boot:
ZynqMP> net list
Could not get PHY for eth0: addr 3
Could not get PHY for eth0: addr 3
eth0 : ethernet@ff0e0000 00:00:00:00:00:00
#9
UltraScale / Re: TE0865-02+TEBT0865+KK0865
Last post by JH - June 27, 2025, 08:38:01 AMHi,
JB1 is pinheader for TE0790 JTAG/UART programmer.It contains FTDI for USB to JTA/UART translation and small Lattice CPLD for IO Pinmapping and voltage level translation.
Links to documentation and dowloads (schematics, CPLD Firmware):
https://wiki.trenz-electronic.de/display/PD/TE0790+Resources
br
John
JB1 is pinheader for TE0790 JTAG/UART programmer.It contains FTDI for USB to JTA/UART translation and small Lattice CPLD for IO Pinmapping and voltage level translation.
Links to documentation and dowloads (schematics, CPLD Firmware):
https://wiki.trenz-electronic.de/display/PD/TE0790+Resources
br
John
#10
UltraScale / Re: Support Request for TE0808...
Last post by cristina - June 24, 2025, 05:53:52 PMQuote from: JH on June 02, 2025, 08:50:31 AMHi,
bitstream itself does not configure PS. This will be done by FSBL, not with bitstream.This is the reason why you didn't see any VIO core, because CLK is missing. In case you want to use PS-PL CLKs and you need only PL part, boot system with your configured PS from SD Card (You can use our prebuilt Boot.bin in case you use the same CLKs like we in our reference design) and overwrite PL over JTAG like you has done above.
br
John
thank you so much, it helped me a lot
