Recent posts

#1

Trenz Electronic FPGA Modules / Re: TE0818 SOM+TEBF0818 Carrie...

Last post by agamboa - March 06, 2026, 07:38:52 AM

Thank you so much for your help, with this I can try and adapt it.

Best regards!

#2

Trenz Electronic FPGA Modules / Re: Issue accessing QSPI Flash...

Last post by M Kirberg - March 05, 2026, 02:51:04 PM

Hi,

does the same thing happen if you use our prebuilt reference design?

To our knowledge similar error in linux occur if the devicetree is not exactly correct (most important properties are frequency, width and parallel-memories entry).

https://wiki.trenz-electronic.de/display/PD/TE0865+Test+Board#TE0865TestBoard-DeviceTree

Please check that the devicetree entries look exactly as those.

#3

Trenz Electronic FPGA Modules / Issue accessing QSPI Flash in ...

Last post by ML TLB - March 05, 2026, 09:44:19 AM

Hi, I have a TE0865-02-DGE43MA module on a TEBT0865-01 carrier board. I'm trying to get it to boot linux using only the QSPI Flash. This fails when u-boot tries to read boot.scr and execute it.

It seems to be an issue in accessing the two QSPI Flashes in x8 dual parallel mode. I tried to look at the content of the QSPI flash by stopping auto-boot and using these commands

Code Select Expand

> sf probe
> sf read 20000000 0 100
> md.b 20000000 100

The read data does not match the first bytes of boot.bin. I can recognize some bytes, but they are shuffled around and half of them are missing, which leads me to believe that it has something to do with the dual parallel flash mode.

Additionally, it detects the wrong flash size of 144MiB.

Code Select Expand

ZynqMP> sf probe
SF: Detected n25q00a with page size 512 Bytes, erase size 128 KiB, total 144 MiB

Now what's really weird, is that if I boot from an SD card containing exactly the same boot.bin, I am able to read the QSPI flash contents correctly, even though it still reports the wrong size.

During QSPI programming, the u-boot that is loaded via jtag from the xilinx installation directory (C:\Xilinx\Vitis\2023.2\data\xicom\cfgmem\uboot\zynqmp_qspi_x8_dual_parallel.bin) correctly identifies the 256MiB Flash size.

I've attached the console output from a SD and QSPI boot with the test outputs.

Any hints?

#4

Trenz Electronic FPGA Modules / Re: TE0715-05-51I33 QSPI verif...

Last post by MA - March 05, 2026, 09:24:54 AM

Hi,

we encountered exactly the same error pattern with an mt25ql256-qspi-x4-single and were able to resolve the issue by adjusting the device tree configuration. Three additional property entries were missing.

I have added an example below for reference:

Code Select Expand

/*------------------ QSPI PHY --------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";

    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;

        spi-rx-bus-width = <4>;
        spi-tx-bus-width = <4>;
        spi-max-frequency = <90000000>;
    };
};
After adding these properties, the QSPI flash operated correctly in x4 mode.

Best regards,
Manuela

#5

Trenz Electronic FPGA Modules / Re: TE0818 SOM+TEBF0818 Carrie...

Last post by Antti Lukats - March 03, 2026, 02:50:14 PM

you can use those MIO pins and main JTAG at the same time. The PJTAG option has never been used as far as I know.

#6

MAX1000 community projects / Re: A few question on the MAX1...

Last post by Antti Lukats - March 03, 2026, 02:48:28 PM

1/ USB has no pins named RX/TX, those are referring on mkr2uno that those pins are default UART pins. For MAX1000 they are just regular FPGA IO pins, use anyway you want, not limited to UART

2/ sorry no. Arduino MKR has AIN pins so we connected them to MAX10 ADC capable pins but never used as ADC

3/ I just now checked from our online shop all schematic links work, just download the schematic there

4/ YES, they are regular IO

5/ We are using some open-source SDRAM controller in our test designs, it works well

#7

MAX1000 community projects / A few question on the MAX1000

Last post by didier@aida.org - March 03, 2026, 02:32:54 PM

Hi

1/  I recently bought a MKR2UNO to use with my MAX1000
    the mkr2uno has 2 pins named TX/RX  are they connected to the usb port in any way

2/  any example somewhere showing how to use ADC with the MAX10000 ?

3/  I saw links to the schematics but they are all dead 
    if there a link working somewhere
    [I would like to build a base board for the MAX 1000]

4/  if I don't want to use the ADC on MAX1000 is it possible to use these pins
    as standard I/O

5/  I saw some questions about sdram controller, I wrote a replica1 / apple 1  in vhdl
    it contains my SDRAM controller as well as a sram to sdram bridge
    usefull top connect al old 6502/6800/6809 core and probably a z80

#8

Trenz Electronic FPGA Modules / Re: TE0818 SOM+TEBF0818 Carrie...

Last post by agamboa - March 02, 2026, 01:09:55 PM

Thank you very much for your help Mr. Lukats,

I think I will need access also to the EX_IO1..4 for other purposes, such as maybe connect another PMOD device.

I have been checking the schematics and the wiki, and I have seen that the EX_IO1..4 are connected to the CPLD Master device. This device only has the MIO26..29 connected to the MPSoC, but these are shared with the PJTAG.

If I manage to edit the code, and connect the EX_IO1..4 to the MIO26..29, will I lose the ability to use the JTAG? At the time I do not use the PJTAG port (J17 or J30 *) of the carrier, and I do not expect to use it, but I do use the JTAG/UART (J12) to reboot the board through the XSCT tool. Would I still be able to debug too?

* PJTAG is mentioned to be connector J17 in this wiki (https://wiki.trenz-electronic.de/display/PD/TEBF0818+CPLD#TEBF0818CPLD-JTAG:~:text=FMC%20JTAG%20Access-,PJTAG,-on%20connector%20J17) and connector J30 on this other wiki (https://wiki.trenz-electronic.de/display/PD/TEBF0818+Getting+Started#TEBF0818GettingStarted-JTAG/UART:~:text=J30%20%2D-,PJTAG,-14)

Best regards.

#9

Trenz Electronic FPGA Modules / Re: TE0818 SOM+TEBF0818 Carrie...

Last post by Antti Lukats - March 02, 2026, 09:06:36 AM

This is great news! Thank you very much!

I was also wondering about the EX_IO1..EX_IO4 outputs of the PMOD connector, these are connected directly to one of the CPLDs on the carrier. Can these pins be managed by the MPSoC? Is the CPLD acting here as a level shifter too?

Best regads.

yes optionally those can be accessed from the FPGA as well, but you would need to modify the CPLD code for that access. So it easier to use EX_IO5..8

#10

Trenz Electronic FPGA Modules / Re: TE0818 SOM+TEBF0818 Carrie...

Last post by agamboa - March 02, 2026, 09:04:15 AM

This is great news! Thank you very much!

I was also wondering about the EX_IO1..EX_IO4 outputs of the PMOD connector, these are connected directly to one of the CPLDs on the carrier. Can these pins be managed by the MPSoC? Is the CPLD acting here as a level shifter too?

Best regads.