Dear Sir,
I am a newbie to vhdl and have written a simple to make use of the two switches S3 and S4 and output to LED D5. However, I did not see it working after I downloaded using the FWU tools. . I have been trying for the the past week without any luck :( .Would you be able to advice.
Thank you and best regards
***** vhdl file ********
entity OR2 is
port (in1, in2: in std_logic;
out1: out std_logic);
end OR2;
architecture behavioral_2 of OR2 is
begin
out1 <= in1 or in2;
end behavioral_2;
********ucf file ***************
NET "in1" LOC = "U23";
NET "in2" LOC = "R22";
NET "out1" LOC = "R20";
Form your UCF section, I assume that you are talking about a Trenz Electronic TE0320 series FPGA module. As you can see from the schematics (SCH-TE0320-00.pdf), push buttons are connected directly to the FPGA input pins. When pressed, the corresponding FPGA input pin senses definitely a low level. To make sure that the FPGA pin senses a high level when released, you have to internally terminate the pin with a pull-up, that otherwise would float.
Please try the following.
********ucf file ***************
# switch S3 = signal PB1 (push button 1)
NET "in1" LOC = "U23" PULLUP;
# switch S4 = signal PB2 (push button 2)
NET "in2" LOC = "R22" PULLUP;
# LED D5 = signal UL1 (user led 1)
NET "out1" LOC = "R20";
I have tested it but after dowloading the code, I did not see the module LED light up at all. I am doing
something wrong ? :-\ There is also an error on the ucf value. I have made the changes and attached below.
# switch S3 = signal PB1 (push button 1)
NET "in1" LOC = "U23" | PULLUP;
# switch S4 = signal PB2 (push button 2)
NET "in2" LOC = "R22" | PULLUP;
# LED D5 = signal UL1 (user led 1)
NET "out1" LOC = "R20";
Do you have a simple example that I can try and download and try ?
Sorry for the small syntax error in the UCF example, and thank you for correcting it.
Yes, we have.
The first thing you have to tell us though is, whether your DONE LED ("TE0320 Series User Manual" > "5.6.1 System LED D1") lights back on after your Firmware Upgrade Tool finishes transferring the FWU file. That would mean that the configuration process of your FPGA completed successfully.
But still you did not tell us anything about your system. Please tell us exactly:
- what HW chain you have (names and versions)
- what SW chain you have (names and versions)
and so on.
I have TE0320-00-EV02IB mounted on TE0323-00 for hardware
as for software, I am using Xilinx 12.2(nt)
the USB firmware upgrade 4.1
Are there any switch setting on the TE board that I need to set ? or any configuration in the xilinx that need to be configure ? ???
Thank you and best regards
Edwin
Hi,
Quote from: thef on October 08, 2010, 04:46:45 AM
Are there any switch setting on the TE board that I need to set ? or any configuration in the xilinx that need to be configure ?
That depends on the problem. Does the DONE LED lit up? If not, then most probably you have to set the startup constraints in ISE to CCLK.
If this setting is correct, then you may have a problem in generating the FWU file.
But without more information, we can only guess.
I strongly recommend to use a JTAG adapter for development. This way you can be sure your bitfile works before building a FWU file.
best regards
Thorsten Trenz
I have a parallel port JTAG, will it work with TE0320 board ? By the way do you have a simple example project that make use of the two switches which you could provide to help me kick start this development.
Danke :)
Hi,
JTAG IO's are powered from VCCAUX, which is 2.5V on your module variant. So if your JTAG cable is capable of 2.5V JTAG chain it will work. In any case, use the Vref on the JTAG connector to power the output drivers of your JTAG cable.
If your JTAG cable is capable of 3.3V JTAG chain only, you can put 220 OHM series resistors between the module and your cable, but this is on your own risk.
Please note, that it is recommended to set the boot mode to JTAG only when using the JTAG cable. See the TE0320 manual for the proper switch positions.
best regards
Thorsten Trenz
Quote from: Horsa on October 07, 2010, 10:16:06 AM
Quote from: thef on October 07, 2010, 09:49:10 AM
Do you have a simple example that I can try and download and try ?
Yes, we have.
top.vhd
-- Trenz Electronic GmbH
-- sample project: tests push buttons and user LEDs
-- version 1.00 (2010-10-09)
-- verified hardware: TE0320-00-EV01
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all; -- recommended library for synthesizable arithmetics
entity top is port (
push_button_1, push_button_2 : in std_logic;
user_led_1, user_led_2, user_led_3, user_led_4 : out std_logic
);
end entity top;
architecture top_architecture of top is
begin
user_led_1 <= not(push_button_2); -- push-buttons_1 is farhter from user_led_1
user_led_2 <= not(push_button_1); -- push-buttons_2 is nearer to user_led_2
user_led_3 <= not(push_button_1) or not(push_button_2); -- logical or -- negative logic
-- user_led_3 <= (push_button_1) nand (push_button_2); -- equivalent logic function
user_led_4 <=
'0' -- turn off test signal when both push buttons are pressed
when (push_button_1 = '0') and (push_button_2 = '0')
else
'1' -- test signal = always on
;
end architecture top_architecture;
# switch S3 = signal PB1 (push button 1)
NET "push_button_1" LOC = "U23" | PULLUP;
# switch S4 = signal PB2 (push button 2)
NET "push_button_2" LOC = "R22" | PULLUP;
# LED D5 = signal UL1 (user led 1)
NET "user_led_1" LOC = "R20";
# LED D6 = signal UL2 (user led 2)
NET "user_led_2" LOC = "V23";
# LED D7 = signal UL3 (user led 3)
NET "user_led_3" LOC = "R19";
# LED D8 = signal UL4 (user led 4)
NET "user_led_4" LOC = "U24";
Xilinx ISE 12.2 project package available upon request. It will be released in the next TE03xx software pack revision.
How do I request for the 12.2 ISE support package ? :)
You did:
http://docs.trenz-electronic.de/Trenz Electronic/TE0320 - Xilinx Spartan-3A DSP industrial-grade FPGA micromodule/sample_projects/ (http://docs.trenz-electronic.de/Trenz%20Electronic/TE0320%20-%20Xilinx%20Spartan-3A%20DSP%20industrial-grade%20FPGA%20micromodule/sample_projects/)
http://docs.trenz-electronic.de/Trenz Electronic/TE0320 - Xilinx Spartan-3A DSP industrial-grade FPGA micromodule/sample_projects/projects-ISE-12-2.pushled.zip (http://docs.trenz-electronic.de/Trenz%20Electronic/TE0320%20-%20Xilinx%20Spartan-3A%20DSP%20industrial-grade%20FPGA%20micromodule/sample_projects/projects-ISE-12-2.pushled.zip)
Please share the outcomes of your investigation.
I have tested the program you gave me and using parallel port JTAG3 from Digilent, I am able to get it to work. However, if I use the FWU tool, the downloaded program just did not work.
One other thing I discover is that if I use the TE00320 v8 the TE0320-00-EV0xB.fwu is able to work, but if I download from another version, the downloaded program fails.
Quote from: thef on October 12, 2010, 10:33:44 AM
I have tested the program you gave me and using parallel port JTAG3 from Digilent, I am able to get it to work.
That is a good news.
Quote from: thef on October 12, 2010, 10:33:44 AM
However, if I use the FWU tool, the downloaded program just did not work.
Can you please document all single steps you perform to build your FWU? And to load it through the FUT?
Quote from: thef on October 12, 2010, 10:33:44 AM
One other thing I discover is that if I use the TE00320 v8 the TE0320-00-EV0xB.fwu is able to work,
That is a good news.
Quote from: thef on October 12, 2010, 10:33:44 AM
but if I download from another version, the downloaded program fails.
Please detail with at least package name, version, path, filename.
Quote from: thef on October 12, 2010, 10:33:44 AM
I have tested the program you gave me and using parallel port JTAG3 from Digilent, I am able to get it to work. However, if I use the FWU tool, the downloaded program just did not work.
Did you set the startup clock to CCLK?
best regards
Thorsten Trenz