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#91

Trenz Electronic FPGA Modules / Re: [TEI0006-04-API23A]: VCCI...

Last post by guirenaud - September 18, 2025, 08:35:09 AM

Hello

I need probably to rephrase my initial post, to give you a bit of context.

I'm using the SOM TEI0006-04-API23A and developping a custom motherboard around it.

It is mentioned in the datasheet (https://wiki.trenz-electronic.de/display/PD/TEI0006+TRM#TEI0006TRM-PowerandPower-OnSequence) that we need to supply 5V for the SOM but with which minimum current ?

Regarding the bank voltages Bank 2K and 2J it is mentioned (rev. v.89 of the online Tec. Ref. Manual)that we can supply VCCIO2J and VCCIO2K in the range from 1.2V to 1.8V. I'm interested to supply it with 3V is it possible ? In theory it should be right?

Sincerely

Guillaume

#92

UltraScale / Re: SFP+ using TEBF08008 and T...

Last post by JH - September 17, 2025, 08:37:23 AM

Hello,
B230_TX/RX2_NP goes to the lower SFP and B230_TX/RX3_NP goes to the upper one.
It is somewhat hidden in the schematic on page 15. You can recognise it by the pin designation. L{1..} for lower and T{1..} for top.

br
John

#93

Trenz Electronic FPGA Modules / [TEI0006-04-API23A]: VCCIO Ba...

Last post by guirenaud - September 16, 2025, 10:46:39 AM

Hello

Regarding VCCIO 2K/2L 3V supplies, can it be supplied with standard 3.3V power module like the one used in the TEIB0006 5V in to 3.3V out (MPM3860GQW-Z)?
Can i use 3.3V supply for VCCIO 2K/2L ?

Sincerely

Guillaume

#94

Trenz Electronic FPGA Modules / Re: [TEI0006-04-API23A]: GX tr...

Last post by guirenaud - September 16, 2025, 09:53:12 AM

Thanks for your quick feedback !

#95

UltraScale / Re: SFP+ using TEBF08008 and T...

Last post by julian05 - September 12, 2025, 04:59:50 PM

Hello,

I am working with the board and I need to clarify how the SFP+ ports are mapped to the physical connectors on the board.

For example, the documentation mentions that the SFP+ interface uses MGT Lane 2 (B230_RX2_P, B230_RX2_N, B230_TX2_P, B230_TX2_N).
Which of the two physical SFP+ cages does this correspond to — the upper one or the lower one?

Thank you in advance for your help.

#96

Trenz Electronic FPGA Modules / Re: CR00103 Certus-NX LiteX no...

Last post by e_tro - September 12, 2025, 11:16:50 AM

Hi, I can't seem to be able to create a new topic, so I post my problem here since it seems related.

I am also having problem booting from flash after writing my own flash image (.mcs)

This is what I have done:
- Compiled i minimum image that sets the green user LED.
- Programmed the FPGA with the .bit file using fast programming. This works as expected and the green led is lit.
- Generated a .mcs file with the following command, genereated by the Deployment tool (<path to project> was replaced with actual path):
"C:/lscc/radiant/2025.1/programmer/bin/nt64/ddtcmd" -oft -advanced -dev "LFD2NX-40" -if "C:/<path to project>/project/impl1/project_impl1.bit" -format int -flashsize 128 -of "C:/<path to project>/project/impl1/project_impl1.mcs"

- Programmed the board with the following settings:

LFD2NX – LFD2NX-40 – Device Properties
Device Operation
Target Memory: External SPI Flash Memory (SPI FLASH)
Port Interface: JTAG2SPI
Access Mode: Direct Programming
Operation: Erase,Program,Verify
Programming Options
Programming file: C:/<path to project>/project_impl1.mcs
SPI Flash Options
Family: SPI Serial Flash
Vendor: Micron
Device: MT25QL128
Package: 8-pin SOP2
SPI Programming
Data file size (Bytes): 142592 (Load from File button visible)
Start address (Hex): 0x00000000
End address (Hex): 0x00020000
<unchecked> Turn off addresses auto updating
<unchecked> Erase SPI part on programming error
<unchecked> Secure SPI flash golden pattern sectors


Programmer output:
INFO <85021074> - Check configuration setup: Start.
INFO <85021077> - Check configuration setup: Successful (Ignored JTAG Connection Checking).
INFO <85021294> - Device1 LFD2NX-40: LFD2NX-40: Refresh Verify ID
INFO <85021298> - Operation Done. No errors.
INFO <85021294> - Device1 LFD2NX-40: MT25QL128: Erase,Program,Verify
Initializing...
IDCode Checking...
Enabling...
Erasing...
Disabling...
Enabling...
Programming...
Disabling...
Verifying...
INFO <85021399> - Execution time: 00 min : 02 sec
INFO <85021371> - Elapsed time: 00 min : 07 sec
INFO <85021373> - Operation: successful.

- After programming, especially erasing, I can see that the stock image has been deleted (no fast blinking green user LED)
- After programming I have tried the reset button and powercycle, but the green LED is no lit.
- After programming and powercycle, the status register is: 0x0000010912800000 and both control registers are 0x0

Can anyone spot the problem?

#97

Trenz Electronic FPGA Modules / Re: UART on TE0711-01

Last post by JH - September 10, 2025, 10:58:33 AM

Hi,
can you tell me which carrier you use?
In case it's one of our carrier, UART is normally on
B2B Connector J1-92 (UART RX with FPGA Pin N17) and J1-85 (UART TX with FPGA Pin R10).

In case you use custom carrier, check also if maybe RX/TX must be swapped?

Can you also check if you use same baudrate in your IP and on your uart console.

br
John

#98

Trenz Electronic FPGA Modules / UART on TE0711-01

Last post by rojeda - September 09, 2025, 02:07:03 PM

Hi guys,

We're using the TE0711-01 board for a "electronic project" and we'd like to use the "Microblaze" to set up the UART interface. Unfortunately, it's not working. Microblaze (softcore) is running, but no TX signal is coming through to the UART.

Based on the example project provided by Trenz Electronic for the board including Microblaze, the following extensions were made.

Here are the steps:

in Vivado (2024.1)
- adding "axi_uartlite_0" -> (regenerate layout & validate design)
- adding tx and rx pins for the hardware config in the "_i_io.xdc"
     
     set_property PACKAGE_PIN K13 [get_ports uart0_txd]
     set_property PACKAGE_PIN K15 [get_ports uart0_rxd]
     set_property IOSTANDARD LVCMOS15 [get_ports uart0_txd]
     set_property IOSTANDARD LVCMOS15 [get_ports uart0_rxd]



- Run Synthesis -> Run Implementation -> Generate Bitstream
- export Hardware Platform (XSA file for Vitis IDE)

in Vitis
- create a platform based on the XSA file provided by Vivado
- create a C app with UART communication,
- debug application work, we can debug step by step but we cannot see any UART TX data on the defined PIN


If needed, the project can also be made available to you.


thanks

#99

Trenz Electronic FPGA Modules / Re: [TEI0006-04-API23A]: GX tr...

Last post by RC - September 05, 2025, 04:13:47 PM

Hello，
We can to share the MAX10 source code with you. You can modify it as needed for your application.
Please email support@trenz-electronic.de so we can send the files as attachments.

According to UG-20070, one refclk can drive multiple channels.

Based on the ATX PLL configuration GUI, 125 MHz should still work well as a reference clock at 12.5 Gbps.

Please feel free to contact us if you encounter any issues.

#100

Trenz Electronic FPGA Modules / Re: TE0720-04 Backwards compat...

Last post by AlexSan - September 04, 2025, 03:08:50 PM

Hello,
our prebuilt files for different hardware versions are generally compatible as far as possible. This always depends on the scope of the hardware changes.

For the TE0720 series, there were no changes affecting the prebuilt files, so you can use the same files for REV04 as for REV03. I therefore assume that your variant is identical for both revisions.

If you are using your own carrier or have modified the CPLD firmware, you may need to take the following PCNs (#8, #18) into account.

• https://wiki.trenz-electronic.de/display/PD/PCN-20220228+TE0720-03+to+TE0720-04+Hardware+Revision+Change

best regards,
Manuela

Hey! Thanks for the anwser! Im using the te0703-06 carrier board without any modifications and from what i understood im good to go!
Have a great evening!